| Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368) |
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| 04/28/2011 | US20110096584 Semiconductor device having open bit line architecture |
| 04/28/2011 | US20110095785 System and method for determination of a horizontal minimum of digital values |
| 04/27/2011 | EP2315211A1 Memory device with serial protocol and corresponding addressing method |
| 04/27/2011 | EP2313891A1 Independently controlled virtual memory devices in memory modules |
| 04/27/2011 | EP2313890A1 Independently controllable and reconfigurable virtual memory devices in memory modules that are pin-compatible with standard memory modules |
| 04/27/2011 | CN1679116B Memory device and system based on processor |
| 04/27/2011 | CN102037515A Memory devices, memory device constructions, constructions, memory device forming methods, current conducting devices, and memory cell programming methods |
| 04/26/2011 | USRE42310 Dual-addressed rectifier storage device |
| 04/26/2011 | US7934234 Transmission and reception of television programmes and other data |
| 04/26/2011 | US7934181 Method and apparatus for improving SRAM cell stability by using boosted word lines |
| 04/26/2011 | US7933162 Row addressing |
| 04/21/2011 | US20110090755 Memory Device Having Multiple Power Modes |
| 04/21/2011 | US20110090749 Circuit for providing chip-select signals to a plurality of ranks of a ddr memory module |
| 04/20/2011 | EP2311037A1 Dynamic power saving memory architecture |
| 04/20/2011 | CN1992074B Row decoder for preventing leakage current and semiconductor memory device having the same |
| 04/20/2011 | CN101202100B Composite store cell |
| 04/19/2011 | US7929372 Decoder, memory system, and physical position converting method thereof |
| 04/19/2011 | US7929359 Embedded DRAM with bias-independent capacitance |
| 04/19/2011 | US7928523 Non-volatile electromechanical field effect devices and circuits using same and methods of forming same |
| 04/14/2011 | WO2010147809A3 Programming reversible resistance switching elements |
| 04/14/2011 | US20110085406 Circuit providing load isolation and memory domain translation for memory module |
| 04/14/2011 | US20110085405 Semiconductor memory device having advanced tag block |
| 04/14/2011 | US20110085404 Semiconductor memory device and information processing system including the same |
| 04/14/2011 | US20110085403 Semiconductor memory device and information processing system including the same |
| 04/14/2011 | US20110085402 Bank re-assignment in chip to reduce ir drop |
| 04/14/2011 | US20110085401 Semiconductor memory device |
| 04/14/2011 | US20110085398 Multiple Cycle Memory Write Completion |
| 04/14/2011 | US20110085397 Semiconductor device and information processing system including the same |
| 04/14/2011 | US20110085394 Latency circuit and semiconductor device comprising same |
| 04/14/2011 | US20110085393 Semiconductor memory apparatus and data input/output method thereof |
| 04/14/2011 | US20110085392 Method for writing data to memory array |
| 04/14/2011 | US20110085389 Method and system to lower the minimum operating voltage of a memory array |
| 04/14/2011 | US20110085367 Switched memory devices |
| 04/13/2011 | CN1675708B Recording method, method of for managing defect in the disc, and recording/reproducing device |
| 04/13/2011 | CN102017003A Method and apparatus for accessing a bidirectional memory |
| 04/13/2011 | CN102017001A Systems and methods for dynamic power savings in electronic memory operation |
| 04/13/2011 | CN101236774B Device and method for single-port memory to realize the multi-port storage function |
| 04/12/2011 | US7924651 Semiconductor storage device and resetting method for a semiconductor storage device |
| 04/12/2011 | US7924630 Techniques for simultaneously driving a plurality of source lines |
| 04/12/2011 | US7924619 Programming method to reduce word line to word line breakdown for NAND flash |
| 04/07/2011 | WO2011038681A1 Point-reading device with on-paper window processing system |
| 04/07/2011 | US20110080771 Dram positive wordline voltage compensation device for array device threshold voltage and voltage compensating method thereof |
| 04/06/2011 | EP2306463A1 Word line compensation in non-volatile memory erase operations |
| 04/06/2011 | CN101364436B Non-volatile memory and method for driving the same |
| 04/06/2011 | CN101164118B Integrated circuit and method for use in integrated circuit memory array |
| 04/06/2011 | CN101023492B Semiconductor memory device with mos transistors each having floating gate and control gate |
| 04/05/2011 | US7920437 Address control circuit of semiconductor memory apparatus |
| 03/31/2011 | US20110078366 Semiconductor device with non-volatile memory and random access memory |
| 03/31/2011 | US20110075505 Semiconductor memory device and layout structure of sub-word line control signal generator |
| 03/31/2011 | US20110075504 Dual Beta Ratio SRAM |
| 03/31/2011 | US20110075503 Main decoding circuit and semiconductor memory apparatus including the same |
| 03/31/2011 | US20110075502 Bank active signal generation circuit |
| 03/31/2011 | US20110075494 Data transfer circuit |
| 03/31/2011 | US20110075470 Embedded sram structure and chip |
| 03/30/2011 | CN1901090B Storage and reproduction apparatus |
| 03/29/2011 | US7916575 Configurable latching for asynchronous memories |
| 03/29/2011 | US7916574 Circuit providing load isolation and memory domain translation for memory module |
| 03/29/2011 | US7916573 Word line block/select circuit with repair address decision unit |
| 03/29/2011 | US7916572 Memory with addressable subword support |
| 03/29/2011 | US7916571 Apparatus for implementing multiple integrated circuits using different gate oxide thicknesses on a single integrated circuit die |
| 03/29/2011 | US7916570 Low power memory device |
| 03/29/2011 | US7916528 Predictive thermal preconditioning and timing control for non-volatile memory cells |
| 03/24/2011 | WO2011034686A2 Configurable memory banks of a memory device |
| 03/24/2011 | US20110069574 Semiconductor memory device |
| 03/24/2011 | US20110069573 Semiconductor memory device |
| 03/24/2011 | US20110069571 Word Line Decoder Circuit Apparatus and Method |
| 03/24/2011 | US20110069560 Data capture system and method, and memory controllers and devices |
| 03/24/2011 | US20110069558 Local word line driver of a memory |
| 03/23/2011 | CN101989463A Bi-directional shift register |
| 03/23/2011 | CN101989453A Column selection circuit of nonvolatile memory read-out circuit and working method thereof |
| 03/23/2011 | CN101989452A Content addressable memory |
| 03/22/2011 | US7911903 Disc with temporary disc definition structure (TDDS) and temporary defect list (TDFL), and method of and apparatus for managing defect in the same |
| 03/22/2011 | US7911875 Address counting circuit and semiconductor memory apparatus using the same |
| 03/22/2011 | US7911874 Semiconductor integrated circuit |
| 03/22/2011 | US7911873 Digital delay locked loop implementation for precise control of timing signals |
| 03/22/2011 | US7911872 Column/row redundancy architecture using latches programmed from a look up table |
| 03/22/2011 | US7911871 Semiconductor memory device operational processing device and storage system |
| 03/22/2011 | US7911867 Semiconductor memory device capable of performing per-bank refresh |
| 03/22/2011 | US7911858 Semiconductor device with DDR memory controller |
| 03/22/2011 | US7911854 Semiconductor memory device |
| 03/22/2011 | US7911825 Multi-port memory based on DRAM core |
| 03/22/2011 | US7911823 Method of programming a non-volatile memory device |
| 03/17/2011 | US20110063933 Semiconductor device, relief-address-information writing device, and relief-address-information writing method |
| 03/17/2011 | US20110063932 Boosting voltage levels applied to an access control line when accessing storage cells in a memory |
| 03/17/2011 | US20110063931 Interfaces, circuits, and methods for communicating with a double data rate memory device |
| 03/17/2011 | US20110063927 Semiconductor device using plural internal operation voltages and data processing system using the same |
| 03/17/2011 | US20110063926 Write Through Speed Up for Memory Circuit |
| 03/17/2011 | US20110063893 Systems and methods for reducing memory array leakage in high capacity memories by selective biasing |
| 03/16/2011 | CN101985733A Target, method for producing the same, memory, and method for producing the same |
| 03/15/2011 | US7908426 Moving sectors within a block of information in a flash memory mass storage architecture |
| 03/15/2011 | US7907473 Semiconductor memory device and data storage method including address conversion circuit to convert coordinate information of data into one-dimensional information to amplifier |
| 03/15/2011 | US7907472 Semiconductor integrated circuit for fetching read data from a DDR-SDRAM operating in synchronization with a clock |
| 03/15/2011 | US7907471 Memory control circuit and semiconductor integrated circuit incorporating the same |
| 03/15/2011 | US7907470 Multi-column addressing mode memory system including an integrated circuit memory device |
| 03/15/2011 | US7907469 Multi-port memory device for buffering between hosts and non-volatile memory devices |
| 03/15/2011 | US7907468 Memory device having data paths permitting array/port consolidation and swapping |
| 03/15/2011 | US7907467 Resistance semiconductor memory device having three-dimensional stack and word line decoding method thereof |
| 03/15/2011 | US7907466 Semiconductor memory apparatus |
| 03/15/2011 | US7907459 Semiconductor memory device and method of testing same |
| 03/15/2011 | US7907446 Nonvolatile semiconductor memory device and method of driving the same |