| Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368) |
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| 03/15/2011 | US7907438 Semiconductor integrated circuit |
| 03/10/2011 | US20110060888 Stacked device remapping and repair |
| 03/10/2011 | US20110058445 Latency counter, semiconductor memory device including the same, and data processing system |
| 03/10/2011 | US20110058444 Latency counter, semiconductor memory device including the same, and data processing system |
| 03/10/2011 | US20110058443 Latency counter, semiconductor memory device including the same, and data processing system |
| 03/10/2011 | US20110058442 Semiconductor device having ODT function and data processing system including the same |
| 03/10/2011 | US20110058441 Data line driving circuit |
| 03/10/2011 | US20110058432 Semiconductor integrated circuit |
| 03/10/2011 | US20110058431 Method and apparatus for compression of configuration bitstream of field programmable logic |
| 03/10/2011 | US20110058421 Systems and Methods for Peak Power and/or EMI Reduction |
| 03/09/2011 | EP2293448A2 Method and apparatus for an N-nary logic circuit |
| 03/09/2011 | EP2291845A1 Systems and methods for dynamic power savings in electronic memory operation |
| 03/08/2011 | US7904767 Semiconductor memory testing device and method of testing semiconductor using the same |
| 03/08/2011 | US7904641 Processor system using synchronous dynamic memory |
| 03/08/2011 | US7903684 Communications architecture for transmission of data between memory bank caches and ports |
| 03/08/2011 | US7903499 Integrated circuit memory devices including delayed clock inputs for input/output buffers and related systems and methods |
| 03/08/2011 | US7903498 Y-decoder and decoding method thereof |
| 03/08/2011 | US7903497 Multi-port SRAM implemented with single-port 6-transistor memory cells coupled to an input multiplexer and an output demultiplexer |
| 03/08/2011 | US7903496 Semiconductor memory device |
| 03/08/2011 | US7903479 Semiconductor memory device |
| 03/03/2011 | WO2011025679A1 3d memory devices decoding and routing systems and methods |
| 03/03/2011 | US20110055671 Advanced memory device having improved performance, reduced power and increased reliability |
| 03/03/2011 | US20110055509 Control component for controlling a delay interval within a memory component |
| 03/03/2011 | US20110051541 Semiconductor device |
| 03/03/2011 | US20110051538 Methods and memory devices for repairing memory cells |
| 03/03/2011 | US20110051537 Address Multiplexing in Pseudo-Dual Port Memory |
| 03/03/2011 | US20110051534 Semiconductor storage device and its control method |
| 03/03/2011 | US20110051530 Semiconductor memory device and method of updating data stored in the semiconductor memory device |
| 03/03/2011 | US20110051529 Memory device |
| 03/03/2011 | US20110051515 Nonvolatile semiconductor memory |
| 03/03/2011 | US20110051512 3d memory devices decoding and routing systems and methods |
| 03/03/2011 | US20110051502 Flexible Word-Line Pulsing For STT-MRAM |
| 03/03/2011 | US20110051483 Content addressable memory array |
| 03/02/2011 | EP2290555A1 Method and apparatus for write protecting a gaming storage medium |
| 03/02/2011 | EP2290551A2 Protocol for communication with dynamic memory |
| 03/02/2011 | EP2290550A2 Protocol for communication with dynamic memory |
| 03/02/2011 | EP2290549A2 Protocol for communication with dynamic memory |
| 03/02/2011 | EP1997112B1 Adjusting a digital delay function of a data memory unit |
| 03/01/2011 | US7900010 System and method for memory allocation management |
| 03/01/2011 | US7898901 Method for controlling clock cycle time for reduced power consumption in a semiconductor memory device |
| 03/01/2011 | US7898900 Latency counter, semiconductor memory device including the same, and data processing system |
| 03/01/2011 | US7898899 Semiconductor integrated circuit and system |
| 03/01/2011 | US7898898 Semiconductor memory apparatus having a sub-word line driver for increasing an area margin in the memory core area |
| 03/01/2011 | US7898896 Semiconductor device |
| 03/01/2011 | US7898895 Semiconductor device |
| 03/01/2011 | US7898894 Static random access memory (SRAM) cells |
| 03/01/2011 | US7898893 Multi-layered memory devices |
| 03/01/2011 | US7898891 Semiconductor memory device |
| 03/01/2011 | US7898883 Method for controlling access of a memory |
| 02/24/2011 | WO2011022114A1 Atomic memory device |
| 02/24/2011 | US20110044123 Circuit and methods for eliminating skew between signals in semicoductor integrated circuit |
| 02/24/2011 | US20110044122 Word line driving apparatus |
| 02/24/2011 | US20110044094 10T SRAM Cell with Near Dual Port Functionality |
| 02/23/2011 | EP2287849A2 Semiconductor memory having dual port cell supporting hidden refresh |
| 02/23/2011 | EP2287743A2 Memory device supporting a dynamically configurable core organisation |
| 02/22/2011 | US7894295 Semiconductor memory device |
| 02/22/2011 | US7894294 Operational mode control in serial-connected memory based on identifier |
| 02/22/2011 | US7894293 Memory bank arrangement for stacked memory |
| 02/17/2011 | US20110038202 Control driver for memory and related method |
| 02/17/2011 | DE102010030742A1 Phasenwechselspeicher in einem doppelreihigen Speichermodul Phase change memory in a double row memory module |
| 02/16/2011 | CN1637940B Semiconductor memory device for high speed data access |
| 02/15/2011 | USRE42145 Write-assisted SRAM bit cell |
| 02/15/2011 | US7890694 Latched address multi-chunk write to EEPROM |
| 02/15/2011 | US7889595 Semiconductor memory device |
| 02/15/2011 | US7889593 Method and apparatus for generating a sequence of clock signals |
| 02/15/2011 | US7889592 Non-volatile memory device and a method of programming the same |
| 02/15/2011 | US7889590 Flash EEPROM system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks |
| 02/15/2011 | US7889589 Memory including periphery circuitry to support a portion or all of the multiple banks of memory cells |
| 02/15/2011 | US7889576 Semiconductor storage device |
| 02/10/2011 | US20110032787 Input buffer circuit, semiconductor memory device and memory system |
| 02/10/2011 | US20110032786 Sub-word line driver circuit and semiconductor memory device having the same |
| 02/10/2011 | US20110032785 Wordline driver, memory device including the same and method of driving a wordline |
| 02/10/2011 | US20110032784 Semiconductor memory with multiple wordline selection |
| 02/10/2011 | US20110032774 Semiconductor Memory With Improved Memory Block Switching |
| 02/10/2011 | US20110032755 Voltage boosting in mram current drivers |
| 02/10/2011 | US20110032751 Semiconductor device |
| 02/09/2011 | CN101971265A Methods for manufacturing a stack of memory circuits and for addressing a memory circuit, corresponding stack and device |
| 02/09/2011 | CN101971263A Address multiplexing in pseudo-dual port memory |
| 02/08/2011 | US7886205 Verification of a data processing system using overlapping address ranges |
| 02/08/2011 | US7885140 Clock mode determination in a memory system |
| 02/08/2011 | US7885139 Multi-chip package |
| 02/08/2011 | US7885138 Three dimensional twisted bitline architecture for multi-port memory |
| 02/08/2011 | US7885136 Semiconductor memory device having high stability and quality of readout operation |
| 02/08/2011 | US7885126 Apparatus for controlling activation of semiconductor integrated circuit |
| 02/08/2011 | US7885123 Integrated circuit for memory card and memory card using the circuit |
| 02/08/2011 | US7885097 Non-volatile memory array with resistive sense element block erase and uni-directional write |
| 02/03/2011 | US20110026355 Interface circuit and semiconductor device incorporating same |
| 02/03/2011 | US20110026354 Current leakage reduction |
| 02/03/2011 | US20110026344 Data control circuit |
| 02/03/2011 | US20110026342 Multi-port memory device |
| 02/03/2011 | US20110026341 Semiconductor memory apparatus |
| 02/03/2011 | US20110026337 Data input/output circuit and semiconductor memory apparatus including the same |
| 02/03/2011 | US20110026308 Cell structure for dual port sram |
| 02/03/2011 | US20110026289 Cell structure for dual port sram |
| 02/03/2011 | DE19852986B4 Schaltungsanordnung und Verfahren zur Datenmaskierung Circuit arrangement and method for data masking |
| 02/02/2011 | CN1787109B Method for controlling data flowing of high speed memory body |
| 02/01/2011 | US7881150 Circuit providing load isolation and memory domain translation for memory module |
| 02/01/2011 | US7881149 Write latency tracking using a delay lock loop in a synchronous DRAM |
| 02/01/2011 | US7881148 Semiconductor memory device |
| 02/01/2011 | US7881147 Clock and control signal generation for high performance memory devices |