Patents
Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368)
02/2011
02/01/2011US7881146 Semiconductor memory apparatus capable of selectively providing decoded row address
02/01/2011US7881145 Semiconductor device and semiconductor system having the same
02/01/2011US7881139 Semiconductor memory device with temperature sensing device and operation thereof
02/01/2011US7881126 Memory structure with word line buffers
01/2011
01/27/2011US20110019495 Decoder circuitry providing forward and reverse modes of memory array operation and method for biasing same
01/27/2011US20110019489 Apparatus and method for data strobe and timing variation detection of an SDRAM interface
01/27/2011US20110019468 Non-linear conductor memory
01/26/2011EP2278474A1 Method and apparatus for coordinating memory operations among diversely-located memory components
01/25/2011US7877566 Simultaneous pipelined read with multiple level cache for improved system performance using flash technology
01/25/2011US7876641 Semiconductor integrated circuit
01/25/2011US7876640 Control voltage tracking circuits, methods for recording a control voltage for a clock synchronization circuit and methods for setting a voltage controlled delay
01/25/2011US7876639 Memory devices having redundant arrays for repair
01/25/2011US7876638 Storing operational information in an array of memory cells
01/20/2011US20110016193 Providing services from a remote computer system to a user station over a communications network
01/20/2011US20110016192 Providing services from a remote computer system to a user station over a communications network
01/20/2011US20110016013 Providing services from a remote computer system to a user station over a communications network
01/20/2011US20110013472 Semiconductor memory device
01/20/2011US20110013470 Structure and Method for Screening SRAMS
01/20/2011US20110013445 Bias Temperature Instability-Influenced Storage Cell
01/20/2011US20110013442 Using storage cells to perform computation
01/19/2011EP2276033A1 A high speed dram architecture with uniform access latency
01/19/2011EP2275943A1 Method and apparatus for coordinating memory operations among diversely-located memory components
01/19/2011CN101950583A Semiconductor memory device having layout area reduced
01/18/2011US7872940 Semiconductor memory device and method for testing the same
01/18/2011US7872939 Semiconductor memory device
01/18/2011US7872938 Soft error robust static random access memory cell storage configuration.
01/18/2011US7872937 Data driver circuit for a dynamic random access memory (DRAM) controller or the like and method therefor
01/18/2011US7872936 System and method for packaged memory
01/18/2011US7872931 Integrated circuit with control circuit for performing retention test
01/18/2011US7872928 Write control signal generation circuit, semiconductor IC having the same and method of driving semiconductor IC
01/18/2011US7872895 Semiconductor device with non-volatile memory and random access memory
01/13/2011US20110007597 Semiconductor Control Line Address Decoding Circuit
01/13/2011US20110007591 Data serializers, output buffers, memory devices and methods of serializing
01/13/2011US20110007590 Semiconductor storage device and method of controlling word line potential
01/13/2011US20110007587 Command latency systems and methods
01/13/2011US20110007583 Semiconductor memory device and internal data transmission method thereof
01/13/2011US20110007576 Synchronous dynamic random access memory semiconductor device for controlling output data
01/13/2011US20110007548 Hierarchical Cross-Point Array of Non-Volatile Memory
01/13/2011DE102004031450B4 Verzögerungsregelkreis-Vorrichtung Delay locked loop device
01/12/2011EP2273376A1 Method and apparatus for coordinating memory operations among diversely-located memory components
01/11/2011US7870362 Semiconductor memory device having advanced tag block
01/11/2011US7869302 Programmable pulsewidth and delay generating circuit for integrated circuits
01/11/2011US7869301 Apparatus for writing to multiple banks of a memory device
01/11/2011US7869288 Output enable signal generating circuit and method of semiconductor memory apparatus
01/11/2011US7869248 Bit line decoder architecture for NOR-type memory array
01/11/2011US7869247 Bit line decoder architecture for NOR-type memory array
01/11/2011US7869246 Bit line decoder architecture for NOR-type memory array
01/06/2011US20110002179 Semiconductor memory device and method for operating the same
01/06/2011US20110002170 Semiconductor memory device having memory block configuration
01/06/2011US20110002159 Semiconductor integrated circuit device
01/05/2011EP2270811A1 Method and apparatus for synchronization of row and column access operations
01/04/2011US7864627 Memory module decoder
01/04/2011US7864625 Optimizing SRAM performance over extended voltage or process range using self-timed calibration of local clock generator
01/04/2011US7864624 Semiconductor memory device and method for operating the same
01/04/2011US7864623 Semiconductor device having latency counter
01/04/2011US7864622 Low power multi-chip semiconductor memory device and chip enable method thereof
01/04/2011US7864621 Compiled memory, ASIC chip, and layout method for compiled memory
01/04/2011US7864620 Partially reconfigurable memory cell arrays
01/04/2011US7864619 Write driver circuit for phase-change memory, memory including the same, and associated methods
01/04/2011US7864618 Semiconductor memory device
01/04/2011US7864579 Integrated circuits having a controller to control a read operation and methods for operating the same
12/2010
12/30/2010US20100329070 Resistance Semiconductor Memory Device Having Three-Dimensional Stack and Word Line Decoding Method Thereof
12/30/2010US20100329069 Semiconductor memory device
12/30/2010US20100329068 Semiconductor memory device
12/30/2010US20100329067 Charge pump and semiconductor device having the same
12/30/2010US20100329066 Non-blocking multi-port memory formed from smaller multi-port memories
12/30/2010US20100329063 Dynamically controlled voltage regulator for a memory
12/30/2010US20100329060 Counter control signal generator and refresh circuit
12/30/2010US20100329053 Semiconductor memory device having a redundancy area
12/30/2010US20100329052 Word line defect detecting device and method thereof
12/30/2010US20100329051 Method and apparatus for synchronization of row and column access operations
12/30/2010US20100329049 Semiconductor memory device having a latency controller
12/30/2010US20100329045 Adjustment of Write Timing in a Memory Device
12/30/2010US20100329044 Assisting write operations to data storage cells
12/30/2010US20100329041 Semiconductor memory device having power-saving effect
12/30/2010US20100329040 Data alignment circuit and method of semiconductor memory apparatus
12/30/2010US20100329039 Data buffer control circuit and semiconductor memory apparatus including the same
12/30/2010US20100329007 Pointer Based Column Selection Techniques in Non-Volatile Memories
12/30/2010US20100328985 Semiconductor device having plural circuit blocks laid out in a matrix form
12/29/2010EP2267724A1 EEPROM memory architecture optimised for embedded memories
12/29/2010EP1639601B1 Asynchronous jitter reduction technique
12/29/2010CN101933095A Non-volatile memory device having configurable page size
12/28/2010US7859940 Semiconductor integrated circuits including clock delay control circuits for non-volatile memories
12/28/2010US7859939 Semiconductor memory device
12/28/2010US7859938 Semiconductor memory device and test method thereof
12/28/2010US7859937 Apparatus and method for controlling write access to a group of storage elements
12/28/2010US7859920 Advanced bit line tracking in high performance memory compilers
12/23/2010US20100322022 Semiconductor storage device
12/23/2010US20100322021 Semiconductor memory device and memory system having the same
12/23/2010US20100321989 Fusion memory device embodied with phase change memory devices having different resistance distributions and data processing system using the same
12/23/2010US20100321988 Cross-point memory devices, electronic systems including cross-point memory devices and methods of accessing a plurality of memory cells in a cross-point memory array
12/23/2010US20100321983 Semiconductor memory device capable of driving non-selected word lines to first and second potentials
12/23/2010US20100321978 Semiconductor memory device and memory cell voltage application method
12/23/2010US20100321977 Programming reversible resistance switching elements
12/22/2010EP2263235A1 Address multiplexing in pseudo-dual port memory
12/22/2010CN101026012B Shift register circuit and image display apparatus having the same
12/21/2010US7855933 Clock synchronization circuit and operation method thereof
12/21/2010US7855932 Low power word line control circuits with boosted voltage output for semiconductor memory
12/21/2010US7855931 Memory system and method using stacked memory device dice, and system using the memory system
12/21/2010US7855923 Write current compensation using word line boosting circuitry
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