Patents
Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368)
04/2012
04/03/2012US8151044 Concurrent memory bank access and refresh retirement
04/03/2012US8149646 Digital filters for semiconductor devices
04/03/2012US8149645 Synchronous global controller for enhanced pipelining
04/03/2012US8149644 Memory system and method that changes voltage and frequency
04/03/2012US8149643 Memory device and method
04/03/2012US8149633 Semiconductor memory device
04/03/2012CA2619358C Content data storage device and its control method
03/2012
03/29/2012US20120075942 Row address decoder and semiconductor memory device having the same
03/29/2012US20120075938 Adaptive and Dynamic Stability Enhancement for Memories
03/29/2012US20120075918 SRAM Having Wordline Up-Level Voltage Adjustable to Assist Bitcell Stability and Design Structure for Same
03/29/2012US20120075902 Identifying and accessing individual memory devices in a memory channel
03/28/2012EP2434492A1 Memory cells having a row-based read and/or write support circuitry
03/28/2012CN102394099A Non- volatile semiconductor memory with page erase
03/27/2012US8144542 Semiconductor memory apparatus and method for operating the same
03/27/2012US8144541 Method and apparatus for adjusting and obtaining a reference voltage
03/27/2012US8144540 Two-port 8T SRAM design
03/27/2012US8144537 Balanced sense amplifier for single ended bitline memory architecture
03/27/2012US8144515 Interleaved flash storage system and method
03/22/2012WO2011103824A3 Timing processing method and circuit for synchronous static random accessible memory (sram)
03/22/2012US20120069692 Semiconductor device
03/21/2012CN1350301B High-speed synchronous semiconductor memory having multi-level line-pipe structure and method of operating the memory
03/20/2012US8140783 Memory system for selectively transmitting command and address signals
03/20/2012US8139438 Semiconductor storage device and memory system
03/20/2012US8139437 Wordline driving circuit of semiconductor memory device
03/20/2012US8139429 Output enable signal generating circuit and method of semiconductor memory apparatus
03/20/2012US8139399 Multiple cycle memory write completion
03/15/2012US20120063256 Memory device word line drivers and methods
03/15/2012US20120063246 Memory controller, memory system including the same, and control method of memory device
03/15/2012US20120063243 Apparatus and method for data capture using a read preamble
03/15/2012US20120063209 Memory device and semiconductor device
03/15/2012US20120063208 Memory device
03/14/2012EP2428960A1 Methods and apparatus for clock signal synchronization in a configuration of series-connected semiconductor devices
03/14/2012EP2428959A1 Semiconductor device
03/13/2012US8134886 Method and apparatus for reducing oscillation in synchronous circuits
03/13/2012US8134885 High-speed compression architecture for memory
03/13/2012US8134884 Semiconductor memory device
03/13/2012US8134876 Data input/output apparatus and method for semiconductor system
03/08/2012US20120057424 Memory Device Having Multiple Power Modes
03/08/2012US20120057421 Devices and system providing reduced quantity of interconnections
03/08/2012US20120057420 Semiconductor memory and method for testing the same
03/08/2012US20120057415 Nonvolatile memory device
03/08/2012US20120057413 Semiconductor memory apparatus and test method thereof
03/08/2012US20120057412 Memory macro configuration and method
03/07/2012EP2426668A1 Flash multi-level threshold distribution scheme
03/07/2012EP1468422B1 Pcram rewrite prevention
03/06/2012USRE43223 Dynamic memory management
03/06/2012US8131883 Method for distributing content to a user station
03/06/2012US8130589 Semiconductor memory device using only single-channel transistor to apply voltage to selected word line
03/06/2012US8130588 Semiconductor memory device having power saving mode
03/06/2012US8130587 Efficient method of replicate memory data with virtual port solution
03/06/2012US8130577 Semiconductor memory device
03/06/2012US8130528 Memory system with sectional data lines
03/01/2012WO2012027080A1 Memory controller with fast reacquisition of read timing to support rank switching
03/01/2012WO2011163022A3 Memory write operation methods and circuits
03/01/2012US20120051172 Shift circuit of a semiconductor device
03/01/2012US20120051171 Channel skewing
03/01/2012US20120051170 Non-volatile memory device
03/01/2012US20120051161 Memory devices and methods of operating memory
03/01/2012US20120051160 Multiple bitcells tracking scheme for semiconductor memories
03/01/2012US20120051155 Process variation compensated multi-chip memory package
03/01/2012US20120051119 Semiconductor device
02/2012
02/29/2012EP2422345A1 Memory system with data line switching scheme
02/29/2012CN101540193B Synchronous memory and method for dynamically actuating address receiver of synchronous memory
02/29/2012CN101401166B Memory device and method having multiple address, data and command buses
02/28/2012US8127069 Memory device including self-ID information
02/28/2012US8125847 Semiconductor memory device and access method thereof
02/28/2012US8125839 Memory device and method reducing fluctuation of read voltage generated during read while write operation
02/28/2012US8125834 Device and method for controlling solid-state memory system
02/28/2012US8125825 Memory system protected from errors due to read disturbance and reading method thereof
02/28/2012US8125251 Semiconductor memory device having a clock alignment training circuit and method for operating the same
02/28/2012US8125211 Apparatus and method for testing driver writeability strength on an integrated circuit
02/28/2012US8125039 One-time programmable, non-volatile field effect devices and methods of making same
02/23/2012US20120044780 Data output circuit of semiconductor memory apparatus
02/22/2012CN1801389B 带有自举存储器电源的高性能寄存器文件和相关方法 Bootstrap memory power performance with the register file and associated methods
02/21/2012US8122275 Write-leveling implementation in programmable logic devices
02/21/2012US8122218 Semiconductor memory asynchronous pipeline
02/21/2012US8120988 Delay locked loop circuit for preventing failure of coarse locking
02/21/2012US8120987 Structure and method for decoding read data-bus with column-steering redundancy
02/21/2012US8120986 Multi-port semiconductor memory device having variable access paths and method therefor
02/21/2012US8120985 Multi-bank memory device method and apparatus
02/16/2012WO2012021568A1 Line termination methods and apparatus
02/16/2012WO2011106262A4 Hierarchical memory architecture
02/16/2012US20120039139 Memory Systems and Methods for Dividing Physical Memory Locations Into Temporal Memory Locations
02/16/2012US20120039138 Asynchronous pipelined memory access
02/16/2012US20120039134 Data output circuit in a semiconductor memory apparatus
02/15/2012EP2417599A1 Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a single-sided word line architecture
02/14/2012US8117363 Memory module capable of improving the integrity of signals transmitted through a data bus and a command/address bus, and a memory system including the same
02/14/2012US8116165 Memory with improved data reliability
02/14/2012US8116164 Semiconductor memory device
02/14/2012US8116144 Memory module having a memory device configurable to different data pin configurations
02/14/2012US8115524 Semiconductor device having auto clock alignment training mode circuit
02/09/2012US20120036315 Morphing Memory Architecture
02/09/2012US20120036303 Apparatus and methods for optically-coupled memory systems
02/09/2012US20120033523 Input circuit of semiconductor memory apparatus and controlling method thereof
02/09/2012US20120033522 Variation-tolerant word-line under-drive scheme for random access memory
02/09/2012US20120033516 Word line driving circuit, semiconductor memory device including the same, and method for testing the semiconductor memory device
02/09/2012US20120033514 Strobe-offset control circuit
02/09/2012US20120033513 Distributed write data drivers for burst access memories
02/09/2012US20120033512 Semiconductor memory device
02/09/2012US20120033509 Memory data reading and writing technique
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