Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 8 - Arrangements for selecting an address in a digital store
Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368)
06/2013
06/26/2013CN103177755A Memory structure containing multiple memory modules and control method thereof
06/26/2013CN103177754A Address decoding circuit for storer
06/25/2013US8472280 Alternate page by page programming scheme
06/25/2013US8472279 Channel skewing
06/25/2013US8472278 Circuits, systems and methods for adjusting clock signals based on measured performance characteristics
06/25/2013US8472277 System and method for memory array decoding
06/25/2013US8472265 Repairing circuit for memory circuit and method thereof and memory circuit using the same
06/20/2013US20130159615 Ddr receiver enable cycle training
06/20/2013US20130155801 Sub word line driver and semiconductor integrated circuit device
06/20/2013US20130155792 Semiconductor device having data terminal supplied with plural write data in serial
06/20/2013US20130155785 Memory macro configuration and method
06/20/2013DE10010440B9 Synchrones dynamisches Speicherbauelement mit wahlfreiem Zugriff und Verfahren zur CAS-Latenzsteuerung Synchronous dynamic random access memory device and method for the CAS latency control
06/19/2013EP2603916A1 Line termination methods and apparatus
06/19/2013CN101140796B 半导体装置 Semiconductor device
06/18/2013US8467263 Memory write operation methods and circuits
06/18/2013US8467262 Method of controlling non-volatile memory device
06/18/2013US8467217 Semiconductor device
06/13/2013WO2013085606A2 Contention-free memory arrangement
06/13/2013US20130148458 Buffer circuit and word line driver using the same
06/13/2013US20130148450 Contention-free memory arrangement
06/13/2013US20130148449 Semiconductor memory device and method for operating the same
06/13/2013US20130148448 Memory system and data transmission method
06/13/2013US20130148445 Local word line driver
06/13/2013US20130148411 Memory device
06/12/2013CN1981275B Method and device for managing a bus
06/12/2013CN103155043A Level shifter with shoot-through current isolation
06/12/2013CN103155042A Decoder circuitry providing forward and reverse modes of memory array operation and method for biasing same
06/12/2013CN101675479B Wear leveling
06/11/2013US8462580 Memory system with reversible resistivity-switching using pulses of alternatrie polarity
06/11/2013US8462579 Method and apparatus for reducing oscillation in synchronous circuits
06/11/2013US8462578 Charge pump circuit with fast start-up
06/11/2013US8462577 Single transistor driver for address lines in a phase change memory and switch (PCMS) array
06/11/2013US8462566 Memory module with termination component
06/11/2013US8462564 Flash memory programming power reduction
06/11/2013US8462561 System and method for interfacing burst mode devices and page mode devices
06/11/2013US8462560 Semiconductor device, method for controlling the same, and semiconductor system
06/11/2013US8462536 Method and apparatus for addressing memory arrays
06/06/2013US20130145233 Memory module and semiconductor storage device
06/06/2013US20130145081 Semiconductor device with non-volatile memory and random access memory
06/06/2013US20130142004 Devices and system providing reduced quantity of interconnections
06/06/2013US20130142003 Dual clock edge triggered memory
06/06/2013US20130142002 Semiconductor Memory Apparatus
06/06/2013US20130141999 Semiconductor integrated circuit
06/06/2013US20130141997 Single-ended volatile memory access
06/06/2013US20130141965 High density semiconductor memory devices
06/06/2013DE102012110303A1 Hochdichte Halbleiterspeichervorrichtung High density semiconductor memory device
06/06/2013DE10016986B4 Halbleiterspeicherbauelement und Verfahren zur Lese-/Schreibsteuerung hierfür The semiconductor memory device and method for reading / writing control for this
06/05/2013CN103137173A High density semiconductor memory devices
06/04/2013US8456946 NAND logic word line selection
06/04/2013US8456945 10T SRAM for graphics processing
06/04/2013US8456926 Memory write error correction circuit
05/2013
05/30/2013US20130135950 Semiconductor memory device and read wait time adjustment method thereof, memory system, and semiconductor device
05/30/2013US20130135947 Semiconductor device having plural selection lines
05/30/2013US20130134393 Nanotube Field Effect Devices and Methods of Making Same
05/29/2013EP2597645A2 Memory module
05/29/2013CN103123803A Semiconductor memory device and driving method thereof
05/28/2013US8451681 Semiconductor storage device including memory cells each having a variable resistance element
05/28/2013US8451680 Method of driving a semiconductor memory device with a sense amplifier controller for maintaining the connection of a previously selected memory cell array
05/23/2013US20130129083 Tamper-resistant memory integrated circuit and encryption circuit using same
05/23/2013US20130128684 Reduced leakage banked wordline header
05/23/2013US20130128683 Semiconductor Devices and Methods for Changing Operating Characteristics and Semiconductor Systems Including the Same
05/22/2013CN103117085A Bias voltage generating circuit and memory of line decoder
05/21/2013USRE44230 Clock signal generation apparatus for use in semiconductor memory device and its method
05/21/2013US8448010 Increasing memory bandwidth in processor-based systems
05/21/2013US8446791 Process tolerant large-swing sense amplfier with latching capability
05/21/2013US8446782 Semiconductor memory device
05/21/2013US8446765 Semiconductor memory device having memory block configuration
05/21/2013US8446755 Multiple cycle memory write completion
05/16/2013US20130121100 Device and method to perform memory operations at a clock domain crossing
05/16/2013US20130121094 Integrated circuit comprising a delay-locked loop
05/16/2013US20130121093 Memory access control device and manufacturing method
05/16/2013US20130121055 Word line driver cell layout for sram and other semiconductor devices
05/16/2013DE102012219907A1 Erhöhen der Speicherkapazität in Systemen mit eingeschränkter elektischer Leistungsaufnahme Increase the storage capacity in systems with reduced power consumption elektischer
05/14/2013USRE44218 Semiconductor memory device for controlling write recovery time
05/14/2013US8441888 Write command and write data timing circuit and methods for timing the same
05/14/2013US8441885 Methods and apparatus for memory word line driver
05/14/2013US8441884 Semiconductor memory device, image processing system, and image processing method
05/14/2013US8441883 Memory arrangement for accessing matrices
05/14/2013US8441882 Memory devices having redundant arrays for repair
05/10/2013WO2013066345A1 Decoder circuits having metal-insulator-metal threshold switches
05/09/2013US20130114366 Semiconductor device having plural selection lines selected based on address signal
05/09/2013US20130114365 Semiconductor memory device and method of driving the same
05/09/2013US20130114358 Address decoding method and semiconductor memory device using the same
05/09/2013US20130114352 Semiconductor memory device
05/08/2013EP2590173A2 Mechanism for peak power management in a memory
05/08/2013EP2590172A2 Semiconductor device including multiple-input logic circuit with operation rate balanced with driving ability
05/08/2013CN103098136A Line termination methods and apparatus
05/08/2013CN103093805A Address decoding method and semiconductor memory device using the same
05/08/2013CN101553876B Non-volatile memory serial core architecture
05/08/2013CN101506896B Method and apparatus for memory array incorporating two data busses for memory array block selection
05/07/2013US8437217 Storing operational information in an array of memory cells
05/07/2013US8437216 Data write training method and semiconductor device performing the same
05/07/2013US8437215 Memory with word-line segment access
05/07/2013US8437211 Semiconductor system and device, and method for controlling refresh operation of stacked chips
05/07/2013US8437203 Nonvolatile memory apparatus and method for processing configuration information thereof
05/07/2013US8437201 Word-line level shift circuit
05/07/2013US8437172 Decoders using memristive switches
05/07/2013US8437163 Memory dies, stacked memories, memory devices and methods
05/02/2013US20130107655 Lookahead Scheme for Prioritized Reads
05/02/2013US20130107644 Storage device, control method of storage device, and control method of storage control device
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