Patents
Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368)
06/2011
06/16/2011US20110141834 Semiconductor device with ddr memory controller
06/16/2011US20110141826 Cache Array Power Savings Through a Design Structure for Valid Bit Detection
06/16/2011US20110141795 Multi-port memory based on dram core
06/16/2011US20110140736 Systems and methods for brain-like information processing
06/15/2011EP2332143A2 Stacked device remapping and repair
06/15/2011EP1668646B1 Method and apparatus for implicit dram precharge
06/15/2011EP1497733B1 Destructive-read random access memory system buffered with destructive-read memory cache
06/15/2011CN1679111B Device writing to a plurality of rows in a memory matrix simultaneously
06/14/2011US7961548 Semiconductor memory device having column decoder
06/14/2011US7961547 Memory device using a common write word line and a common read bit line
06/09/2011US20110134715 Method for accessing vertically stacked embedded non-flash re-writable non-volatile memory
06/09/2011US20110134712 Apparatus and method for trimming static delay of a synchronizing circuit
06/09/2011US20110134706 Semiconductor memory device
06/09/2011DE10125724B4 Speichersystem, Speicherbauelement und Speicherdatenzugriffsverfahren Memory system, the memory device and memory data access method
06/08/2011EP2330594A1 Non volatile logic devices using magnetic tunnel junctions
06/08/2011EP2329498A1 Dual power scheme in memory circuit
06/08/2011EP2329497A2 Dynamic real-time delay characterization and configuration
06/08/2011CN1729539B Method and device for protection of an MRAM device against tampering
06/08/2011CN1584774B 半导体集成电路 The semiconductor integrated circuit
06/07/2011US7957218 Memory controller with skew control and method
06/07/2011US7957217 Method of controlling internal voltage and multi-chip package memory prepared using the same
06/07/2011US7957216 Common memory device for variable device width and scalable pre-fetch and page size
06/07/2011US7957215 Method and apparatus for generating temperature-compensated read and verify operations in flash memories
06/07/2011US7957211 Method and apparatus for synchronization of row and column access operations
06/07/2011US7957209 Method of operating a memory apparatus, memory device and memory apparatus
06/07/2011US7957204 Flash memory programming power reduction
06/07/2011US7957178 Storage cell having buffer circuit for driving the bitline
06/03/2011WO2011044385A3 Vertically stackable dies having chip identifier structures
06/02/2011US20110128811 Internal command generation circuit
06/02/2011US20110128810 Memory device and memory control for controlling the same
06/02/2011US20110128809 Method and Apparatus of Addressing A Memory Integrated Circuit
06/02/2011US20110128807 Memory device and sense circuitry therefor
06/02/2011US20110128802 Semiconductor memory device
06/02/2011US20110128800 Semiconductor memory apparatus
06/02/2011US20110128772 Nonvolatile memory cells and nonvolatile memory devices including the same
06/01/2011DE112004002973B4 Halbleiterbauelement und Verfahren zum Schreiben von Daten A semiconductor device and method for writing data
06/01/2011DE102010038063A1 Speicher mit dazwischen geschaltetem Transistor Memory with intervening switched transistor
06/01/2011CN1652248B Method and memory system in which operating mode is set using address signal
06/01/2011CN102084380A Electronic system for emulating the chain of the DNA structure of a chromosome
05/2011
05/31/2011US7952958 Non-volatile semiconductor storage system
05/31/2011US7952957 Circuit for generating read and signal and circuit for generating internal clock using the same
05/31/2011US7952956 Variable resistance memory device and system
05/31/2011US7952955 Semiconductor memory
05/31/2011US7952954 Semiconductor integrated circuit for generating row main signal and controlling method thereof
05/31/2011US7952953 Semiconductor memory device and memory system including the same
05/31/2011US7952952 Reduction of fusible links and associated circuitry on memory dies
05/31/2011US7952945 Method and apparatus for determining write leveling delay for memory interfaces
05/26/2011WO2011062680A2 Memory device and method thereof
05/26/2011US20110122721 Y-Decoder and Decoding Method Thereof
05/26/2011US20110122712 Controlling voltage levels applied to access devices when accessing storage cells in a memory
05/26/2011US20110122710 Method and apparatus for generating a sequence of clock signals
05/26/2011US20110121867 High-speed compression architecture for memory
05/26/2011DE10394263B4 Verfahren zur Herstellung einer integrierten Schaltung A method of fabricating an integrated circuit
05/25/2011EP2325752A2 Memory device supporting a dynamically configurable core organisation
05/25/2011CN102077289A Dynamic power saving memory architecture
05/24/2011US7948824 Self reset clock buffer in memory devices
05/24/2011US7948823 Semiconductor memory device and word line driving method thereof
05/24/2011US7948819 Integrated circuit having a memory with process-voltage-temperature control
05/19/2011US20110116337 Synchronising between clock domains
05/19/2011US20110116336 Multi-layered memory devices
05/19/2011US20110116335 Semiconductor memory device and system including the same
05/19/2011US20110116331 Method for initializing memory device
05/17/2011US7944773 Synchronous command-based write recovery time auto-precharge control
05/17/2011US7944772 Semiconductor memory device and method for generating output enable signal
05/17/2011US7944771 Semiconductor integrated circuit and method of processing address and command signals thereof
05/12/2011WO2011056281A1 Three-dimensional memory array stacking structure
05/12/2011US20110110176 Address control circuit and semiconductor memory device
05/12/2011US20110110174 System and Method of Operating a Memory Device
05/12/2011US20110110165 Clock mode determination in a memory system
05/11/2011EP1788578B1 Non-volatile storage device and control method thereof
05/10/2011US7940600 Non-volatile memory with stray magnetic field compensation
05/10/2011US7940599 Dual port memory device
05/10/2011US7940598 Integrated circuit memory device, system and method having interleaved row and column control
05/10/2011US7940597 Semiconductor memory device and parallel test method of the same
05/10/2011US7940575 Memory device and method providing logic connections for data transfer
05/10/2011US7940564 Three-dimensional memory device with multi-plane architecture
05/10/2011US7940555 Row decoder for non-volatile memory devices, in particular of the phase-change type
05/05/2011US20110103171 Semiconductor memory apparatus
05/05/2011US20110103165 Self-refresh test circuit of semiconductor memory apparatus
05/05/2011US20110103162 Semiconductor memory apparatus
05/05/2011US20110103160 Semiconductor memory apparatus
05/05/2011US20110103130 Resistance change memory device
05/05/2011US20110103127 And-type one time programmable memory cell
05/05/2011US20110103121 Stacked semiconductor device and automatic chip recognition selection circuit
05/05/2011DE102010039223A1 Steuereinheit, Halbleiterspeicherelement und Halbleiterspeichersystem Controller semiconductor memory device and semiconductor memory system
05/04/2011CN1934528B Memory card that provides non-volatile data storage and method for reading data from the storage card
05/04/2011CN1828767B Memory address generating circuit and memory controller using the same
05/04/2011CN1637952B Data strobe circuit using clock signal
05/04/2011CN102047340A Apparatus and method for multi-phase clock generation
05/04/2011CN102047339A Memory cell employing reduced voltage
05/04/2011CN102044288A Method for converting electrical address and topological address of memory
05/03/2011US7936639 System and method for processing signals in high speed DRAM
05/03/2011US7936638 Enhanced programmable pulsewidth modulating circuit for array clock generation
05/03/2011US7936637 System and method for synchronizing asynchronous signals without external clock
05/03/2011US7936636 Semiconductor memory device and method for reducing current consumption by controlling toggling of clock
05/03/2011US7936635 Semiconductor memory device and method for driving the same
05/03/2011US7936634 Memory control circuit and memory accessing method
05/03/2011US7936581 Bit line decoder architecture for nor-type memory array
04/2011
04/28/2011WO2011049753A1 Memory having internal processors and methods of controlling memory access
04/28/2011US20110096615 Memory devices having redundant arrays for repair
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