Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 8 - Arrangements for selecting an address in a digital store
Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368)
11/2011
11/01/2011US8050073 Semiconductor memory device
10/2011
10/27/2011WO2011131511A1 Dynamic read/write memory device having improved word line control circuitry
10/27/2011US20110261640 Semiconductor memory device and data processing system including the semiconductor memory device
10/27/2011US20110261636 Common memory device for variable device width and scalable pre-fetch and page size
10/27/2011US20110261633 Memory with improved data reliability
10/27/2011US20110261617 Semiconductor memory device having memory block configuration
10/25/2011US8045416 Method and memory device providing reduced quantity of interconnections
10/25/2011US8045413 High speed DRAM architecture with uniform access latency
10/25/2011US8045408 Semiconductor integrated circuit with multi test
10/25/2011US8045407 Memory-write timing calibration including generation of multiple delayed timing signals
10/25/2011US8045406 Latency circuit using division method related to CAS latency and semiconductor memory device
10/20/2011US20110255362 Read command triggered synchronization circuitry
10/20/2011US20110255361 Multi-port memory having a variable number of used write ports
10/20/2011US20110255354 Semiconductor integrated circuit
10/19/2011EP1949381B1 Pseudo-dual port memory where ratio of first to second memory access is clock duty cycle independent
10/18/2011US8040753 System and method for capturing data signals using a data strobe signal
10/18/2011US8040752 Counter circuit, latency counter, semiconductor memory device including the same, and data processing system
10/18/2011US8040751 Semiconductor memory device
10/18/2011US8040711 Apparatus and methods for optically-coupled memory systems
10/13/2011WO2011126619A1 Methods and apparatus for transmission of data
10/13/2011US20110249525 Circuits, Systems and Methods for Adjusting Clock Signals Based on Measured Performance Characteristics
10/13/2011US20110249522 Method and circuit for calibrating data capture in a memory controller
10/13/2011US20110249521 Semiconductor device
10/12/2011CN1905059B Multi-port memory based on DRAM core and controlling method thereof
10/12/2011CN102214481A Multi-level cell flash memory reading-writing method and device and storage device
10/11/2011US8037440 Optimization of ROM structure by splitting
10/11/2011US8036062 Semiconductor memory device and method for driving the same
10/11/2011US8036061 Integrated circuit with multiported memory supercell and data path switching circuitry
10/11/2011US8036049 Semiconductor memory device including a global input/output line of a data transfer path and its surrounding circuits
10/06/2011WO2011095792A3 Method of addressing an array and data storage devices addressable by such a method
10/06/2011WO2011059611A3 Memory arrays and associated methods of manufacturing
10/06/2011US20110242929 Semiconductor memory apparatus
10/06/2011US20110242928 Address delay circuit of semiconductor memory apparatus
10/06/2011US20110242927 Encoded Read-Only Memory (ROM) Decoder
10/06/2011US20110242926 PSEUDO-INVERTER CIRCUIT ON SeO1
10/06/2011US20110242925 Reduction of fusible links and associated circuitry on memory dies
10/06/2011US20110242924 Semiconductor memory device and method of controlling the same
10/06/2011US20110242923 Semiconductor memory device including clock control circuit and method for operating the same
10/06/2011US20110242912 Random Access Memory Devices Having Word Line Drivers Therein That Support Variable-Frequency Clock Signals
10/06/2011US20110242910 Data strobe clock buffer in semiconductor memory apparatus, method of controlling the same, and semiconductor apparatus having the same
10/06/2011US20110242909 Semiconductor device and system
10/06/2011US20110242908 Command decoder and a semiconductor memory device including the same
10/06/2011US20110242869 Three-dimensional stacked semiconductor integrated circuit and control method thereof
10/05/2011EP2372716A1 Pseudo-inverter circuit on SeOI
10/05/2011EP2370975A1 Clock-forwarding low-power signaling system
10/05/2011CN102209989A Dynamic real-time delay characterization and configuration
10/05/2011CN101196954B Circuit having relaxed setup time via reciprocal clock and data gating
10/04/2011US8031554 Circuit and method for controlling loading of write data in semiconductor memory device
10/04/2011US8031553 Data strobe signal generating device and a semiconductor memory apparatus using the same
10/04/2011US8031552 Multi-port memory device with serial input/output interface
10/04/2011US8031546 Semiconductor device
09/2011
09/29/2011WO2011119938A1 Reference cell write operations in a memory
09/29/2011WO2011119647A1 Multi-port non-volatile memory that includes a resistive memory element
09/29/2011WO2011119641A1 Multiple instruction streams memory system
09/29/2011WO2011116678A1 Interactive presentation system of electronic reading device with on-paper window system
09/29/2011US20110238931 Memory device, memory system and microcontroller including memory device, and memory control device
09/29/2011US20110235459 Clock-forwarding low-power signaling system
09/29/2011US20110235458 Electric device
09/29/2011US20110235446 Write strobe generation for a memory interface controller
09/29/2011US20110235406 Low-Power 5T SRAM with Improved Stability and Reduced Bitcell Size
09/29/2011US20110235387 Semiconductor memory device
09/29/2011DE19645745B4 Dynamischer Schreib-/Lesespeicher Dynamic read / write memory
09/28/2011EP2368246A1 Method, system and apparatus for tri-stating unused data bytes during ddr dram writes
09/28/2011CN102203867A Volatile memory elements with soft error upset immunity
09/27/2011US8027222 Burst mode control circuit
09/27/2011US8027221 Memory device
09/27/2011US8027220 Oscillation device, method of oscillation, and memory device
09/27/2011US8027219 Semiconductor memory devices having signal delay controller and methods performed therein
09/27/2011US8027218 Processor instruction cache with dual-read modes
09/27/2011US8027216 Semiconductor memory device
09/27/2011US8027205 Semiconductor memory device and operation method thereof
09/27/2011US8027192 Resistive memory devices using assymetrical bitline charging and discharging
09/27/2011US8027190 Command processing circuit and phase change memory device using the same
09/27/2011US8026921 Driving method, driving circuit and driving apparatus for a display system
09/22/2011US20110228627 Double data rate memory device having data selection circuit and data paths
09/22/2011US20110228626 Synchronization circuit and method with transparent latches
09/22/2011US20110228625 Write command and write data timing circuit and methods for timing the same
09/22/2011US20110228624 Sub-word-line driving circuit, semiconductor memory device having the same, and method of controlling the same
09/22/2011US20110228619 Memory control apparatus and mask timing adjusting method
09/22/2011US20110228618 System with controller and memory
09/22/2011US20110228616 Clock Generator Circuits with Non-Volatile Memory for Storing and/or Feedback-Controlling Phase and Frequency
09/22/2011US20110228614 Memory System Topologies Including A Buffer Device And An Integrated Circuit Memory Device
09/22/2011US20110228595 Memory Cell That Includes Multiple Non-Volatile Memories
09/22/2011US20110228594 Multi-Port Non-Volatile Memory that Includes a Resistive Memory Element
09/20/2011US8024399 Software distribution over a network
09/20/2011US8023358 System and method for providing a non-power-of-two burst length in a memory system
09/20/2011US8023357 Address converting circuit and semiconductor memory device using the same
09/20/2011US8023353 Semiconductor memory device, refresh control method thereof, and test method thereof
09/20/2011US8023314 Dynamic memory word line driver scheme
09/15/2011US20110225475 Low overhead and timing improved architecture for performing error checking and correction for memories and buses in system-on-chips, and other circuits, systems and processes
09/15/2011US20110222358 Memory Systems and Methods for Dynamically Phase Adjusting A Write Strobe and Data To Account for Receive-Clock Drift
09/15/2011US20110222332 Fully Balanced Dual-Port Memory Cell
09/15/2011US20110221474 Non-binary decoder architecture and control signal logic for reduced circuit complexity
09/15/2011US20110221007 Semiconductor memory device
09/14/2011CN1892914B Circuit and method for driving word line
09/13/2011US8019932 Block management for mass storage
09/13/2011US8019589 Memory apparatus operable to perform a power-saving operation
09/13/2011US8019194 Digital audio and video recording and storage system and method
09/13/2011US8018791 Circuit, system and method for controlling read latency
09/13/2011US8018790 Serial memory interface
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