Patents
Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368)
07/2011
07/28/2011DE102010024480A1 Integrierte Schaltungen und Verfahren zum Herstellen derselben Integrated circuits and methods for manufacturing the same
07/27/2011EP2347418A1 Logical unit operation
07/26/2011US7986584 Memory device having multiple power modes
07/26/2011US7986583 Method for designing integrated circuit incorporating memory macro
07/26/2011US7986582 Method of operating a memory apparatus, memory device and memory apparatus
07/26/2011US7986577 Precharge voltage supplying circuit
07/26/2011US7986570 Very small swing high performance asynchronous CMOS static memory (multi-port register file) with power reducing column multiplexing scheme
07/26/2011US7986542 Semiconductor memory apparatus
07/21/2011US20110176376 Low power synchronous memory command address scheme
07/21/2011US20110176375 Semiconductor memory device for reducing ripple noise of back-bias voltage and method of driving semiconductor memory device
07/21/2011US20110176374 Bist ddr memory interface circuit and method for testing the same
07/21/2011DE10032122B4 Halbleiterspeicherbauelement mit Redundanzschaltkreis The semiconductor memory device with redundancy circuit
07/20/2011CN102129880A Three-dimensional chip selection sharing input package
07/19/2011US7984207 Dynamically setting burst length of double data rate memory device by applying signal to at least one external pin during a read or write transaction
07/19/2011US7983112 Semiconductor device which transmits or receives a signal to or from an external memory by a DDR system
07/19/2011US7983111 Memory controller for controlling memory and method of controlling memory
07/19/2011US7983110 Circuit and method for controlling a clock synchronizing circuit for low power refresh operation
07/19/2011US7983109 Semiconductor device
07/19/2011US7983108 Row mask addressing
07/19/2011US7983103 Semiconductor memory device suitable for mounting on portable terminal
07/19/2011US7983101 Circuit for generating data strobe signal in DDR memory device and method therefor
07/19/2011US7983094 PVT compensated auto-calibration scheme for DDR3
07/19/2011US7982505 Logic circuit, address decoder circuit and semiconductor memory
07/14/2011WO2011062680A3 Memory device and method thereof
07/14/2011US20110170366 Temperature detector in an integrated circuit
07/14/2011US20110170365 Row addressing
07/14/2011US20110170353 Access line dependent biasing schemes
07/13/2011CN102124525A Virtual memory interface
07/12/2011US7978562 Semiconductor memory device
07/12/2011US7978561 Semiconductor memory devices having vertically-stacked transistors therein
07/12/2011US7978538 Setting memory device termination in a memory device and memory controller interface in a communication bus
07/12/2011US7978533 NAND flash memory with a programming voltage held dynamically in a NAND chain channel region
07/07/2011WO2011080771A1 Timing violation handling in a synchronous interface memory
07/07/2011WO2011080768A1 Memory devices comprising partitions with particular ecc attributes
07/07/2011US20110167211 Dram controller for video signal processing operable to enable/disable burst transfer
07/07/2011US20110167204 Memory block identified by group of logical block addresses, storage device with movable sectors, and methods
07/07/2011US20110164463 Structure and Method for Decoding Read Data-Bus With Column-Steering Redundancy
07/07/2011US20110164461 Memory Device
07/07/2011US20110164460 Semiconductor device and method of controlling the same
07/06/2011CN102117650A Character line driver of storage circuit device
07/05/2011US7975164 DDR memory controller
07/05/2011US7975162 Apparatus for aligning input data in semiconductor memory device
07/05/2011US7975125 Method for read-only memory devices
07/05/2011US7974149 Thin-film memory system equipped with a thin-film address decoder and memory controller
07/05/2011US7974148 Semiconductor memory device using only single-channel transistor to apply voltage to selected word line
07/05/2011US7974147 Method and apparatus for monitoring memory addresses
07/05/2011US7974146 Wordline temperature compensation
07/05/2011US7974145 Semiconductor memory device using bus inversion scheme
07/05/2011US7974143 Memory system, a memory device, a memory controller and method thereof
07/05/2011US7974141 Setting memory device VREF in a memory controller and memory device interface in a communication bus
07/05/2011US7974121 Write current compensation using word line boosting circuitry
06/2011
06/30/2011US20110161581 Semiconductor circuit apparatus
06/30/2011US20110158033 Semiconductor memory device
06/30/2011US20110158032 Clock control circuit and clock generation circuit including the same
06/30/2011US20110158031 Signal calibration methods and apparatuses
06/30/2011US20110158030 Method and apparatus for tuning phase of clock signal
06/30/2011US20110158029 Word line driving circuit and semiconductor storage device
06/30/2011US20110158028 Block decoder of semiconductor memory device
06/30/2011US20110158024 Semiconductor memory device and method for operating the same
06/30/2011US20110158020 Circuit and method for controlling precharge in semiconductor memory apparatus
06/30/2011US20110158019 Semiconductor memory device and operation method thereof
06/30/2011US20110158014 Burst address generator and test apparatus including the same
06/30/2011US20110158012 Semiconductor memory device having redundancy circuit for repairing defective unit cell
06/30/2011US20110158010 Skew detector and semiconductor memory device using the same
06/30/2011US20110158009 Apparatus for generating output data strobe signal
06/30/2011US20110157968 Semiconductor memory device
06/30/2011US20110157963 Sram word-line coupling noise restriction
06/30/2011US20110157960 Nonvolatile Memory Devices and Related Methods and Systems
06/29/2011CN1777955B Methods for contracting conducting layers overlying magnetoelectronic elements of MRAM devices
06/29/2011CN102113056A Dual power scheme in memory circuit
06/28/2011US7969816 Memory device
06/28/2011US7969815 System and method for controlling timing of output signals
06/28/2011US7969814 Read command triggered synchronization circuitry
06/28/2011US7969813 Write command and write data timing circuit and methods for timing the same
06/28/2011US7969812 Semiconductor control line address decoding circuit
06/28/2011US7969811 Semiconductor memory device highly integrated in direction of columns
06/28/2011US7969799 Multiple memory standard physical layer macro function
06/28/2011US7969766 Semiconductor memory device
06/28/2011US7969765 Sense amplifier for semiconductor memory device
06/28/2011US7969400 Liquid crystal display device with decreased power consumption
06/28/2011US7969201 Decoder circuit
06/28/2011US7969200 Decoder circuit
06/23/2011WO2011034686A3 Configurable memory banks of a memory device
06/23/2011US20110149675 Local Word Line Driver
06/23/2011US20110149674 Integrated circuit memory with word line driving helper circuits
06/23/2011US20110149673 Three State Word Line Driver ForA DRAM Memory Device
06/23/2011US20110149667 Reduced area memory array by using sense amplifier as write driver
06/23/2011US20110149661 Memory array having extended write operation
06/23/2011US20110149629 Semiconductor Memory Apparatus and Method of Operating the Same
06/21/2011US7965582 Circuit and method for recovering clock data in highly integrated semiconductor memory apparatus
06/21/2011US7965581 System with controller and memory
06/21/2011US7965580 Method and apparatus for reducing oscillation in synchronous circuits
06/21/2011US7965577 Word line defect detecting device and method thereof
06/21/2011US7965576 Apparatus for testing memory device
06/21/2011US7965575 Semiconductor memory device and method of providing product families of the same
06/21/2011US7965552 Non-volatile semiconductor memory device
06/16/2011WO2011069780A1 Cache access memory and method
06/16/2011US20110141841 Synchronous semiconductor memory device having on-die termination circuit and on-die termination method
06/16/2011US20110141840 Nor-or decoder
06/16/2011US20110141836 Techniques for reducing impact of array disturbs in a semiconductor memory device
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