Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 8 - Arrangements for selecting an address in a digital store
Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368)
09/2011
09/13/2011US8018784 Semiconductor device and data processor
09/13/2011US8018767 Semiconductor device and method of controlling the same
09/08/2011US20110216621 Synchronous Command-Based Write Recovery Time Auto Precharge Control
09/08/2011US20110216620 Decoder circuit
09/08/2011US20110216615 Semiconductor memory device highly integrated in direction of columns
09/08/2011US20110216611 Method and apparatus for calibrating write timing in a memory system
09/07/2011EP2363861A1 Memory device with mode-selectable prefetch and clock-to-core timing
09/07/2011CN102177553A A bridging device having a configurable virtual page size
09/07/2011CN102177552A Stacked device remapping and repair
09/07/2011CN102177551A Independently controllable and reconfigurable virtual memory devices in memory modules that are pin-compatible with standard memory modules
09/07/2011CN102177550A Independently controlled virtual memory devices in memory modules
09/06/2011US8014227 Burst length control circuit and semiconductor memory device using the same
09/06/2011US8014214 Semiconductor memory device
09/01/2011WO2011106262A2 Hierarchical memory architecture
09/01/2011US20110211417 Memory device with pseudo double clock signals and the method using the same
09/01/2011US20110211416 Circuit and method for recovering clock data in highly integrated semiconductor memory apparatus
09/01/2011US20110211415 Integrated Circuit Memory Device, System And Method Having Interleaved Row And Column Control
09/01/2011US20110211414 Semiconductor memory module
09/01/2011US20110211413 Semiconductor memory device and method for operating the same
09/01/2011US20110211411 Semiconductor device, information processing system including same, and controller for controlling semiconductor device
09/01/2011US20110211398 Memory device and associated main word line and word line driving circuit
08/2011
08/31/2011EP2362398A1 SRAM with different supply voltages for memory cells and access logic circuitry
08/31/2011CN102169725A Memory device and system based on processor
08/30/2011USRE42659 Large-capacity semiconductor memory with improved layout for sub-amplifiers to increase speed
08/30/2011US8009506 Memory architecture having multiple partial wordline drivers and contacted and feed-through bitlines
08/30/2011US8009505 Semiconductor memory device
08/30/2011US8009504 Semiconductor memory input/output device
08/30/2011US8009503 Card controller controlling semiconductor memory including memory cell having charge accumulation layer and control gate
08/30/2011US8009485 Semiconductor memory device
08/30/2011US8009462 SRAM architecture
08/30/2011US8009457 Write current compensation using word line boosting circuitry
08/25/2011US20110205832 On-die termination circuit, memory device, memory module, and method of operating and training an on-die termination
08/25/2011US20110205831 System and method for processing signals in high speed dram
08/25/2011US20110205830 Semiconductor Control Line Address Decoding Circuit
08/25/2011US20110205829 Semiconductor memory device
08/25/2011US20110205828 Semiconductor memory with memory cell portions having different access speeds
08/25/2011US20110205824 Data processing system
08/25/2011US20110205818 Semiconductor memory device, memory system including the same, and method for adjusting timing between internal clock and command
08/24/2011EP2359369A1 Semiconductor device with main memory unit and auxiliary memory unit requiring preset operation
08/24/2011CN102163546A 半导体器件及其制造方法 Semiconductor device and manufacturing method thereof
08/23/2011US8005995 Command interface systems and methods
08/23/2011US8004929 Semiconductor memory device and control method thereof
08/23/2011US8004928 Active driver control circuit for semiconductor memory apparatus
08/23/2011US8004927 Reversible-polarity decoder circuit and method
08/23/2011US8004926 System and method for memory array decoding
08/23/2011US8004925 Variable resistive memory
08/18/2011WO2011099961A1 Memory resistor adjustment using feedback control
08/18/2011US20110199851 Memory controller, semiconductor storage device, and memory system including the memory controller and the semiconductor storage device
08/18/2011US20110199846 Y-decode controlled dual rail memory
08/18/2011US20110199844 Semiconductor Memory Device Suitable for Mounting on a Portable Terminal
08/18/2011US20110199837 High Voltage Word Line Driver
08/17/2011EP2357653A2 Stacked memory device and method thereof
08/17/2011EP2356657A1 Mesochronous signaling system with multiple power modes
08/17/2011CN1967719B Programmable logic device memory elements with elevated power supply levels
08/17/2011CN1677555B Data storage unit, data storage controlling apparatus and method
08/16/2011US8001410 Efficient clocking scheme for ultra high-speed systems
08/16/2011US8001325 Memory card that supports file system interoperability
08/16/2011US8000166 Semiconductor memory device and operating method thereof
08/16/2011US8000165 Self reset clock buffer in memory devices
08/16/2011US8000164 Self refresh operation of semiconductor memory device
08/16/2011US8000163 Self refresh operation of semiconductor memory device
08/16/2011US8000162 Voltage-controlled oscillator, phase-locked loop, and memory device
08/16/2011US8000159 Semiconductor memory device having memory block configuration
08/16/2011US8000144 Method and system for accessing a flash memory device
08/16/2011US8000143 Nonvolatile memory device including circuit formed of thin film transistors
08/16/2011US7999869 Random access decoder
08/11/2011WO2011097457A1 Systems and methods for writing to multiple port memory circuits
08/11/2011WO2011095792A2 Method of addressing an array and data storage devices addressable by such a method
08/11/2011US20110194370 Memory Having Asynchronous Read With Fast Read Output
08/11/2011US20110194364 Nvm overlapping write method
08/11/2011US20110194362 Word-line driver using level shifter at local control circuit
08/11/2011US20110194333 System and Method to Select a Reference Cell
08/11/2011US20110193592 Voltage level shifter with dynamic circuit structure having discharge delay tracking
08/11/2011DE102011000542A1 Überlappendes Schreibverfahren eines NVM Overlapping writing method of NVM
08/10/2011EP2353165A1 Data protection during power-up in spin transfer torque magnetoresistive random access memory
08/10/2011EP2353164A1 Word line voltage control in stt-mram
08/09/2011US7995422 Burst order control circuit and method thereof
08/09/2011US7995421 Semiconductor memory device with a sense amplifier controller for maintaining the connection of a previously selected memory cell array
08/09/2011US7995420 User selectable banks for DRAM
08/09/2011US7995419 Semiconductor memory and memory system
08/09/2011US7995417 Semiconductor memory circuit
08/04/2011US20110188335 Hierarchical Multi-Bank Multi-Port Memory Organization
08/04/2011US20110188332 Semiconductor memory device having regular area and spare area
08/04/2011US20110188328 Systems and Methods for Writing to Multiple Port Memory Circuits
08/04/2011US20110188326 Dual rail static random access memory
08/04/2011US20110188322 Memory device with data paths for outputting compressed data
08/04/2011US20110188282 Memory architectures and techniques to enhance throughput for cross-point arrays
08/04/2011US20110188281 Local bit lines and methods of selecting the same to access memory elements in cross-point arrays
08/03/2011EP2351044A1 Data transfer and programming in a memory device
08/03/2011EP2351038A2 Common memory device for variable device width and scalable pre-fetch and page size
08/03/2011EP2351036A1 A bridging device having a configurable virtual page size
08/03/2011EP2351035A1 Switched interface stacked-die memory architecture
08/03/2011EP1979911B1 Tunneling-resistor-junction-based microscale/nanoscale demultiplexer arrays
08/03/2011CN101206908B Memory device, memory controller and memory system
08/02/2011US7990802 Selective edge phase mixing
08/02/2011US7990801 Internal write/read pulse generating circuit of a semiconductor memory apparatus
08/02/2011US7990800 Circuit and method for controlling DRAM column-command address
08/02/2011US7990799 Semiconductor memory device that includes an address coding method for a multi-word line test
08/02/2011US7990798 Integrated circuit including a memory module having a plurality of memory banks
07/2011
07/28/2011US20110182128 Asynchronous/synchronous interface
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