Patents
Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368)
03/2013
03/12/2013US8395963 Data security for dynamic random access memory at power-up
03/12/2013US8395962 Semiconductor memory device and method for operating the same
03/12/2013US8395961 Semiconductor memory device
03/12/2013US8395960 Memory circuits having a plurality of keepers
03/12/2013US8395959 Storage device, control method of storage device, and control method of storage control device
03/12/2013US8395951 Memory controller
03/07/2013US20130058179 System and method for increasing ddr memory bandwidth in ddr sdram modules
03/07/2013US20130058175 Ddr psram and data writing and reading methods thereof
03/07/2013US20130058174 Controller and access method for ddr psram and operating method thereof
03/06/2013EP2564388A1 Non-volatile memory and method with even/odd combined interleaved block decoding with adapted word line activation circuitry
03/06/2013CN102959639A Method and apparatus for training memory signal via error signal of memory
03/06/2013CN102959633A Memory write operation methods and circuits
03/06/2013CN101727961B Imbedded reconfigurable memorizer in programmable gate array
03/05/2013US8392673 Data writing/reading method, a de-interleaving method, a data processing method, a memory and a memory drive apparatus
03/05/2013US8391100 Semiconductor memory apparatus
03/05/2013US8391099 Integrated circuit memory device, system and method having interleaved row and column control
03/05/2013US8391098 Data input/output circuit and method of semiconductor memory apparatus
02/2013
02/28/2013WO2013003655A3 Deselect drivers for a memory array
02/28/2013WO2013002868A3 Circuits and methods for memory
02/28/2013US20130051171 Memory refresh methods, memory section control circuits, and apparatuses
02/28/2013US20130051167 Semiconductor memory device and defective cell relieving method
02/28/2013US20130051137 Tile-level snapback detection through coupling capacitor in a cross point array
02/28/2013DE102012107577A1 Multiport-Speicherelement sowie Halbleitervorrichtung und System mit demselben Multi-port memory element and semiconductor device and with the same system
02/26/2013US8386747 Processor and method for dynamic and selective alteration of address translation
02/26/2013US8385150 Delay efficient gater repeater
02/26/2013US8384427 Configuring multiple programmable logic devices with serial peripheral interfaces
02/21/2013WO2013025262A2 Memory devices and methods for high random transaction rate
02/21/2013US20130044558 Memory device and method
02/21/2013US20130044553 Integrated circuit, system including the same, and operation method of the system
02/21/2013US20130044552 Strobe-offset control circuit
02/21/2013DE102005046997B4 Vorrichtung zum Speichern von Speicherwörtern Means for storing memory words
02/20/2013CN102939632A Memory arrays
02/19/2013US8379480 Non-volatile memory device and method of manufacturing the same
02/19/2013US8379478 Synchronous global controller for enhanced pipelining
02/19/2013US8379477 Sub-word-line driving circuit, semiconductor memory device having the same, and method of controlling the same
02/19/2013US8379476 Semiconductor memory device for reducing ripple noise of back-bias voltage and method of driving semiconductor memory device
02/19/2013US8379475 Clock control circuit and clock generation circuit including the same
02/19/2013US8379474 Word line selection circuit and row decoder
02/19/2013US8379473 Semiconductor memory device and method for operating the same
02/19/2013US8379459 Memory system with delay locked loop (DLL) bypass control
02/19/2013US8379448 Memory with interleaved read and redundant columns
02/19/2013US8379428 Semiconductor storage device and method of manufacturing the same
02/14/2013US20130039144 Multiple device apparatus, systems, and methods
02/14/2013US20130039143 Semiconductor memory device, semiconductor system including the semiconductor memory device, and method for operating the semiconductor memory device
02/14/2013US20130039142 Input buffer circuit, semiconductor memory device and memory system
02/13/2013CN101985733B Target, method for producing the same, memory, and method for producing the same
02/13/2013CN101506897B Dual data-dependent busses for coupling read/write circuits to a memory array
02/12/2013US8374052 Information storage devices using magnetic domain wall movement and methods of operating the same
02/12/2013US8374051 Three dimensional memory system with column pipeline
02/12/2013US8374050 Multi-port memory using single-port memory cells
02/12/2013US8373442 Selector circuit and processor system
02/07/2013US20130033954 Memory Buffers and Modules Supporting Dynamic Point-to-Point Connections
02/07/2013US20130033947 Clock generator
02/07/2013US20130033946 Frequency-agile strobe window generation
02/07/2013US20130033945 System and method for interfacing burst mode devices and page mode devices
02/07/2013US20130033942 System-in package including semiconductor memory device and method for determining input/output pins of system-in package
02/05/2013US8369182 Delay locked loop implementation in a synchronous dynamic random access memory
02/05/2013US8369180 Memory word line boost using thin dielectric capacitor
02/05/2013US8369179 Semiconductor module including module control circuit and method for controlling the same
02/05/2013US8369178 System and method for managing self-refresh in a multi-rank memory
02/05/2013US8369177 Techniques for reading from and/or writing to a semiconductor memory device
02/05/2013US8369168 Devices and system providing reduced quantity of interconnections
02/05/2013US8369160 Data output circuit of semiconductor memory and related method
02/05/2013US8369138 Semiconductor memory device for reading out data stored in memory
02/05/2013US8369122 Semiconductor apparatus
01/2013
01/31/2013WO2013016495A1 Apparatuses and methods including memory array data line selection
01/31/2013WO2013016295A1 Gather method and apparatus for media processing accelerators
01/31/2013WO2013015893A1 Memory with deferred fractional row activation
01/31/2013US20130028041 Memory Compression
01/31/2013US20130028014 Reference voltage generators and sensing circuits
01/31/2013US20130027084 Apparatus and method for decoding an address in two stages
01/31/2013DE10108922B4 Elektronische Speicheranordnung Electronic storage device
01/30/2013EP2550658A1 Multi-port non-volatile memory that includes a resistive memory element
01/30/2013EP2550657A1 Reference cell write operations in a memory
01/30/2013EP2550656A1 Multiple instruction streams memory system
01/29/2013US8363508 Semiconductor device having ODT function and data processing system including the same
01/29/2013US8363507 Wordline driver, memory device including the same and method of driving a wordline
01/29/2013US8363506 Semiconductor memory device
01/29/2013US8363505 Local word line driver
01/24/2013US20130021866 Semiconductor Devices Compatible with Mono-Rank and Multi-Ranks
01/24/2013US20130021858 Process Variability Tolerant Programmable Memory Controller for a Pipelined Memory System
01/24/2013DE102012106454A1 Halbleiterbauelemente, die zu Mono- und Multi-Ranks kompatibel sind Semiconductor devices that are compatible with single and multi-Ranks
01/24/2013DE102011108172A1 Speichersystem und Verfahren zum Übermitteln von Konfigurationsbefehlen Memory system and method for transmitting configuration commands
01/24/2013DE102011107936A1 Halbleitervorrichtung und Verfahren für die Ablaufverfolgung elnes Speichers einer Halbleitervorrichtung Semiconductor device and method for tracing ELNES memory of a semiconductor device
01/23/2013CN102891147A 记忆体结构 Memory structure
01/22/2013US8359445 Method and apparatus for signaling between devices of a memory system
01/22/2013US8358558 Address control circuit and semiconductor memory device
01/22/2013US8358557 Memory device and method
01/22/2013US8358547 Delay-locked-loop circuit, semiconductor device and memory system having the delay-locked-loop circuit
01/22/2013US8358532 Word-line driver including pull-up resistor and pull-down transistor
01/16/2013CN1988035B Multi-path accessible semiconductor memory device and its operation method
01/16/2013CN102884578A Techniques for refreshing a semiconductor memory device
01/15/2013US8355294 Synchronous data processing system for reliable transfer of data irrespective of propagation delays and process, voltage and temperature (PVT) variations
01/10/2013WO2012154638A3 Dynamic data caches, decoders and decoding methods
01/10/2013US20130010564 Semiconductor memory device
01/10/2013US20130010556 Semiconductor memory device, method of controlling read preamble signal thereof, and data transmission system
01/10/2013US20130010553 Semiconductor memory device, method of controlling read preamble signal thereof, and data transmission system
01/10/2013US20130010552 Multi-mode memory device and method having stacked memory dice, a logic die and a command processing circuit and operating in direct and indirect modes
01/10/2013US20130010546 Apparatus and method for receiving a differential data strobe signal
01/08/2013US8351284 Delay locked loop
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