Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 8 - Arrangements for selecting an address in a digital store
Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368)
08/2003
08/21/2003US20030156464 Semiconductor memory device operating in synchronization with clock signal
08/21/2003US20030156462 Memory devices having power supply routing for delay locked loops that counteracts power noise effects
08/20/2003EP1336970A2 Memory cell and wordline driver for embedded dram in asic process
08/19/2003US6609236 Semiconductor IC device having a memory and a logic circuit implemented with a single chip
08/19/2003US6609174 Embedded MRAMs including dual read ports
08/19/2003US6609160 Selector with group identification terminals
08/19/2003US6608796 Circuit configuration for controlling the word lines of a memory matrix
08/19/2003US6608795 Semiconductor device including memory with reduced current consumption
08/19/2003US6608793 Efficient management method of memory cell array
08/19/2003US6608791 Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions
08/19/2003US6608780 High performance semiconductor memory devices
08/19/2003US6608775 Register file scheme
08/19/2003US6608743 Delay locked loop, synchronizing method for the same and semiconductor device equipped with the same
08/14/2003WO2003067599A1 Multiple write-port memory
08/14/2003US20030154347 Methods and apparatus for reducing processor power consumption
08/14/2003US20030151968 User selectable banks for DRAM
08/14/2003US20030151966 High speed DRAM architecture with uniform access latency
08/14/2003US20030151964 Semiconductor memory and control method
08/14/2003US20030151958 Semiconductor memory device having booster circuits
08/14/2003US20030151957 Dual bandgap voltage reference system and method for reducing current consumption during a standby mode of operation and for providing reference stability during an active mode of operation
08/14/2003US20030151948 Asymmetric band-gap engineered nonvolatile memory device
08/14/2003US20030151939 Methods and apparatus for accessing configuration data
08/14/2003US20030151072 DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same
08/14/2003US20030151071 DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same
08/14/2003US20030151070 Booster circuit for non-volatile semiconductor memory device
08/13/2003EP1335384A1 Inner voltage level control circuit, semiconductor storage, and method for controlling them
08/13/2003EP0968465B1 Television or radio control system development for mpeg
08/13/2003EP0876708B1 An address transition detection circuit
08/13/2003CN1435845A Non-Volatile semiconductor memory with charging read mode
08/13/2003CN1435843A Synchronous semiconductor memory apparatus with plurality of memory sets and method for controlling same
08/13/2003CN1118068C Register file read/write cell
08/12/2003US6606277 Semiconductor memory device
08/12/2003US6606276 SRAM device using MIS transistors
08/12/2003US6606275 High performance semiconductor memory devices
08/07/2003WO2003019801A3 Method for reproducing multimedia files in a terminal
08/07/2003WO2002078003A3 Method and apparatus for biasing selected and unselected array lines when writing a memory array
08/07/2003US20030149831 Decoding structure for a memory device with a control code
08/07/2003US20030147287 Nonvolatile semiconductor memory with power-up read mode
08/06/2003EP1046172B1 Device containing a multi-port memory
08/06/2003CN1434454A Method for constructing multi-counter, multi-counter and multi-queue device using same
08/06/2003CN1434453A Method for realizing two first-in first-out queue using one double-port RAM
08/06/2003CN1117379C Field programmable memory array
08/06/2003CN1117377C Shared bootstrap circuit
08/05/2003US6603705 Method of allowing random access to rambus DRAM for short burst of data
08/05/2003US6603704 Reduced current address selection circuit and method
08/05/2003US6603703 Dynamic memory word line driver scheme
08/05/2003US6603702 Semiconductor integrated circuit
08/05/2003US6603700 Non-volatile semiconductor memory device having reduced power requirements
08/05/2003US6603692 Semiconductor memory device improving data read-out access
08/05/2003US6603687 Semiconductor devices, circuits and methods for synchronizing the inputting and outputting data by internal clock signals derived from single feedback loop
08/05/2003US6603684 Semiconductor memory device having noise tolerant input buffer
08/05/2003US6603683 Decoding scheme for a stacked bank architecture
08/05/2003US6603338 Device and method for address input buffering
08/05/2003US6603334 Low-amplitude driver circuit
07/2003
07/31/2003WO2003063208A2 Array-based architecture for molecular electronics
07/31/2003US20030145184 DRAM having SRAM equivalent interface
07/31/2003US20030142577 Synchronous semiconductor memory device with a plurality of memory banks and method of controlling the same
07/31/2003US20030142576 Semiconductor integrated circuit device
07/31/2003US20030142575 Hole driver in semiconductor memory device
07/31/2003US20030142531 Apparatus and method for driving ferroelectric memory
07/31/2003US20030142530 Memory cell with fuse element
07/31/2003US20030141896 Method and apparatus for low capacitance, high output impedance driver
07/30/2003EP1330828A2 Upscaled clock feeds memory to make parallel waves
07/30/2003EP1330715A2 Storing device, storing control method and program
07/30/2003EP1129409A4 Redundant form address decoder for memory system
07/30/2003CN1433028A Semiconductor device, circuit and method with synchronous input and output data
07/30/2003CN1433026A Semiconductor memroy containing delay circuit capable of generating sufficiently stable delay signal
07/30/2003CN1116684C Word line driver storage using the same and method of reducing voltage source energy consumption
07/29/2003US6601130 Memory interface unit with programmable strobes to select different memory devices
07/29/2003US6601077 DSP unit for multi-level global accumulation
07/29/2003US6600692 Semiconductor device with a voltage regulator
07/29/2003US6600679 Level shifter for converting a voltage level and a semiconductor memory device having the level shifter
07/29/2003US6600342 Column decoder of semiconductor memory device
07/29/2003US6600337 Line segmentation in programmable logic devices having redundancy circuitry
07/24/2003WO2003060921A1 Memory cell circuit, memory device, motion vector detection device, and motion compensation prediction coding device.
07/24/2003WO2003060687A2 Device for storing data and method for dividing space for data storing
07/24/2003US20030140290 Synchronous semiconductor device, and inspection system and method for the same
07/24/2003US20030140289 Dual port RAM
07/24/2003US20030140206 Non-volatile semiconductor memory with a function for preventing unauthorized reading
07/24/2003US20030137889 Method for discharging word line and semicondcutor memory device using the same
07/24/2003US20030137875 Non-volatile semiconductor memory device
07/24/2003US20030137873 Read disturb alleviated flash memory
07/24/2003US20030136976 Nonvolatile semiconductor memory with a page mode
07/23/2003EP1329901A1 Memory cell with fuse element
07/23/2003EP1329896A1 Semiconductor memory and control method
07/23/2003CN1432153A Dual-ported cams for simultaneous operation flash memory
07/22/2003US6598171 Integrated circuit I/O using a high performance bus interface
07/22/2003US6598116 Memory interface using only one address strobe line
07/22/2003US6597629 Built-in precision shutdown apparatus for effectuating self-referenced access timing scheme
07/22/2003US6597627 Clock switching circuitry for avoiding conflict of data handling occuring in a memory
07/22/2003US6597625 Semiconductor memory device
07/22/2003US6597624 Semiconductor memory device having hierarchical word line structure
07/22/2003US6597623 Low power architecture for register files
07/22/2003US6597622 Apparatus and method for operation of multi-bank semiconductor memory device with an up/down counter
07/22/2003US6597621 Multi-bank semiconductor memory device
07/22/2003US6597616 DRAM core refresh with reduced spike current
07/22/2003US6597201 Dynamic predecoder circuitry for memory circuits
07/22/2003US6597037 Programmable memory address decode array with vertical transistors
07/17/2003WO2003058634A1 Pcram rewrite prevention
07/17/2003WO2003058629A1 Memory controller with ac power reduction through non-return-to-idle of address and control signals
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