Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 8 - Arrangements for selecting an address in a digital store
Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368)
11/2003
11/06/2003US20030206432 Minimizing errors in a magnetoresistive solid-state storage device
11/05/2003EP1359588A2 Memory architecture for increased speed and reduced power consumption
11/05/2003EP1287528B1 Semiconductor memory and controlling method thereof
11/05/2003EP1233372A9 Circuit and method for protecting a chip arrangement against manipulation and/or against abuse
11/05/2003CN1453797A 半导体存储器 Semiconductor memory
11/04/2003US6643216 Asynchronous queuing circuit for DRAM external RAS accesses
11/04/2003US6643215 Synchronous memory devices with synchronized latency control circuits and methods of operating same
11/04/2003US6643213 Write pulse circuit for a magnetic memory
11/04/2003US6643211 Integrated memory having a plurality of memory cell arrays
11/04/2003US6643210 Semiconductor integrated circuit device and method of controlling the same
11/04/2003US6643208 Semiconductor integrated circuit device having hierarchical power source arrangement
11/04/2003US6643204 Self-time scheme to reduce cycle time for memories
11/04/2003US6643191 Semiconductor device having chip selection circuit and method of generating chip selection signal
11/04/2003US6643180 Semiconductor memory device with test mode
11/04/2003US6643176 Reference current generation circuit for multiple bit flash memory
11/04/2003US6643172 Bit line decoding scheme and circuit for dual bit memory with a dual bit selection
11/04/2003US6642098 DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same
10/2003
10/30/2003US20030204688 Method and apparatus for selectively transmitting command signal and address signal
10/30/2003US20030204667 Destructive-read random access memory system buffered with destructive-read memory cache
10/30/2003US20030202416 Semiconductor storing device for reading out or writing data from/in memory cells
10/30/2003US20030202415 Driver control circuit
10/30/2003US20030202405 High performance semiconductor memory devices
10/30/2003US20030202404 Memory device with row and column decoder circuits arranged in a checkboard pattern under a plurality of memory arrays
10/30/2003US20030202377 Flash EEprom system
10/30/2003US20030202374 Semiconductor memory device
10/30/2003US20030201817 Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions
10/30/2003US20030201793 Line segmentation in programmable logic devices having redundancy circuitry
10/29/2003CN1452178A 半导体存储器件 A semiconductor memory device
10/29/2003CN1452176A Semiconductor memory delay circuit
10/29/2003CN1126111C Global wire management apparatus and method for multiple port random access memory
10/28/2003US6640295 Semiconductor circuit with address translation circuit that enables quick serial access in row or column directions
10/28/2003US6639870 Address transition detecting circuit
10/28/2003US6639869 Clock-synchronous semiconductor memory device
10/28/2003US6639867 Decoder circuit in a semiconductor memory device
10/28/2003US6639866 Very small swing high performance asynchronous CMOS static memory (multi-port register file) with power reducing column multiplexing scheme
10/28/2003US6639865 Memory device, method of accessing the memory device, and reed-solomon decoder including the memory device
10/28/2003US6639850 Semiconductor integrated circuit having latching means capable of scanning
10/28/2003US6639822 Dynamic ram-and semiconductor device
10/28/2003US6639821 Memory circuit with memory elements overlying driver cells
10/28/2003US6639427 High-voltage switching device and application to a non-volatile memory
10/23/2003WO2002099809A3 Method and device for masking out non-serviceable memory cells
10/23/2003US20030200521 Array-based architecture for molecular electronics
10/23/2003US20030200417 Process for controlling reading data from a DRAM array
10/23/2003US20030200416 Synchronous dram system with control data
10/23/2003US20030200415 Synchronous data transfer system
10/23/2003US20030200381 Synchronous DRAM with control data buffer
10/23/2003US20030200380 Latched address multi-chunk write to EEPROM
10/23/2003US20030198121 Semiconductor memory device
10/23/2003US20030198120 Multi-port memory circuit
10/23/2003US20030198101 Word line selector for a semiconductor memory
10/23/2003US20030198100 Method of controlling the operation of non-volatile semiconductor memory chips
10/23/2003US20030198094 Multi-port memory cell
10/23/2003US20030198090 Fully hidden refresh dynamic random access memory
10/23/2003US20030198083 Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics
10/23/2003US20030198070 Dense content addressable memory cell
10/23/2003DE10203152C1 Semiconductor memory device has driver transistor pair for each memory module and coupling transistor for coupling adjacent memory row selection lines
10/22/2003EP1258007B1 Wordline driver for flash memory read mode
10/22/2003EP1252631B1 High performance cmos word-line driver
10/22/2003EP1118937B1 Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics
10/22/2003EP1105877B1 Memory system
10/22/2003CN1450563A Semiconductor IC device and method for generating read out starting action signal
10/21/2003US6636453 Memory circuit having a plurality of memory areas
10/21/2003US6636452 Address control apparatus of semiconductor memory device using bank address
10/21/2003US6636448 Semiconductor memory device having fewer memory cell plates being activated in a test mode than in a normal mode
10/21/2003US6636446 Semiconductor memory device having write latency operation and method thereof
10/21/2003US6636444 Semiconductor memory device having improved data transfer rate without providing a register for holding write data
10/21/2003US6636207 Display driver IC
10/21/2003US6636096 Upscaled clock feeds memory to make parallel waves
10/16/2003WO2003085672A1 Memory chip architecture having non-rectangular memory banks and method for arranging memory banks
10/16/2003WO2003038829A3 Storage assembly
10/16/2003WO2002069342A3 Method and apparatus for off boundary memory access
10/16/2003US20030196070 Process of operating a DRAM system
10/16/2003US20030196069 Process of using a dram with address control data
10/16/2003US20030196068 Memory device for transferring streams of data
10/16/2003US20030196067 RAM with fewer address terminals than data terminals
10/16/2003US20030196034 Synchronous data system with control data buffer
10/16/2003US20030193832 Semiconductor memory apparatus simultaneously accessible via multi-ports
10/16/2003US20030193830 Wordline driven method for sensing data in a resistive memory array
10/16/2003US20030193359 Semiconductor memory delay circuit
10/15/2003EP1352393A1 Techniques to asynchronously operate a synchronous memory
10/15/2003CN1449567A Word line decoding architecture in a flash memory
10/15/2003CN1449050A Semiconductor storage apparatus
10/15/2003CN1448943A Magnetic storage device
10/15/2003CN1124612C Semiconductor storage device and method for boosting word line of the device
10/15/2003CN1124609C Semiconductor memory
10/14/2003US6633949 Bank selector circuit for a simultaneous operation flash memory device with a flexible bank partition architecture
10/14/2003US6633505 Semiconductor memory device, control method thereof, and control method of semiconductor device
10/09/2003WO2003083669A2 Inexact addressable digital memory
10/09/2003US20030189869 Semiconductor integrated circuit device having hierarchical power source arrangement
10/09/2003US20030189864 Methods and devices for increasing voltages on non-selected wordlines during erasure of a flash memory
10/09/2003US20030189859 Timer circuit and semiconductor memory incorporating the timer circuit
10/09/2003US20030189856 Multi-level flash memory with temperature compensation
10/09/2003US20030189848 Memory address generator with scheduled write and read address generating capability
10/09/2003US20030189845 Semiconductor device having redundancy circuit
10/09/2003DE10216909C1 Transistor voltage level converter circuit for memory decoding circuits has input and output lines and outputs voltage level lower than low state and voltage level higher than high state
10/09/2003CA2479944A1 Digital memory
10/08/2003CN1447974A Method and appts. for synchronzation of row and column access operation
10/08/2003CN1447432A 半导体存储器 Semiconductor memory
10/08/2003CN1123891C Memory device and method thereof
10/07/2003US6631094 Semiconductor memory device having SRAM interface
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