Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
04/2005
04/06/2005EP1521269A2 Asymmetric patterned magnetic memory
04/06/2005EP1521230A2 Electron emitter display device having micro-display array, amplifying circuit, memory device, analog switch, and current control unit
04/06/2005EP1521179A1 Phase controlled high speed interfaces
04/06/2005EP1218888A4 A symmetric segmented memory array architecture
04/06/2005CN1605106A Segmented write line architecture
04/06/2005CN1605105A Low power auto-refresh circuit and method for dynamic random access memories
04/06/2005CN1605104A Apparatus and methods for nondestructive data storage and retrieval
04/06/2005CN1604463A Differential amplifier and bit-line sense amplifier adopting the same
04/06/2005CN1604337A Information processing structure
04/06/2005CN1604336A Information processing structure
04/06/2005CN1604332A Integrated storage circuit
04/06/2005CN1604235A Testing device possessing static storage device and testing method
04/06/2005CN1604232A Method to improve cache capacity of soi and bulk
04/06/2005CN1604231A 存储器 Memory
04/06/2005CN1604230A Peripheral circuit balanced drive magnetic random access memory
04/06/2005CN1604229A Magnetic memory device and method of manufacturing magnetic memory device
04/06/2005CN1604228A Magnetic random memory storing unit with low write-in current characteristic and method for making same
04/06/2005CN1603468A Dry etching method for magnetic material
04/06/2005CN1196198C Semiconductor memory unit
04/06/2005CN1196136C Semiconductor storage device
04/06/2005CN1196135C Integrated circuit device with synchronous signal generator
04/06/2005CN1196133C Dram incorporating self refresh control circuit and system LSI including the dram
04/06/2005CN1196132C Memory cell arrangement and operational method therefor
04/06/2005CN1196131C Method for revising defective tunnel node
04/05/2005US6877078 Information processing system with memory element performance-dependent memory control
04/05/2005US6877064 Triggering of IO equilibrating ending signal with firing of column access signal
04/05/2005US6876595 Decode path gated low active power SRAM
04/05/2005US6876594 Integrated circuit with programmable fuse array
04/05/2005US6876593 Method and apparatus for partial refreshing of DRAMS
04/05/2005US6876592 Semiconductor memory device
04/05/2005US6876589 Method and apparatus for supplementary command bus
04/05/2005US6876587 Semiconductor memory device
04/05/2005US6876585 Circuit and method for selecting reference voltages in semiconductor memory device
04/05/2005US6876580 Semiconductor memory device having a burst continuous read function
04/05/2005US6876578 Semiconductor memory device for storing multivalued data
04/05/2005US6876577 Programming method of nonvolatile semiconductor memory device
04/05/2005US6876576 Thin film magnetic memory device having redundant configuration
04/05/2005US6876575 Thin film magnetic memory device having a magnetic tunnel junction
04/05/2005US6876574 Magnetoresistive device and electronic device
04/05/2005US6876573 Semiconductor memory device
04/05/2005US6876572 Programmable logic devices with stabilized configuration cells for reduced soft error rates
04/05/2005US6876571 Static random access memory having leakage reduction circuit
04/05/2005US6876569 Semiconductor integrated circuit device with improved storage MOSFET arrangement
04/05/2005US6876568 Timing adjusting circuit and semiconductor memory device
04/05/2005US6876567 Ferroelectric memory device and method of reading a ferroelectric memory
04/05/2005US6876564 Integrated circuit device and method for applying different types of signals to internal circuit via one pin
04/05/2005US6876523 Magnetic head, and the magnetic read-write devices, and the magnetic memory with magnetic sensors
04/05/2005US6876247 High voltage generator without latch-up phenomenon
04/05/2005US6876226 Integrated digital circuit
04/05/2005US6876030 Semiconductor memory device
04/05/2005US6876022 Junction-isolated depletion mode ferroelectric memory devices
04/05/2005US6874866 Ink jet nozzle having an actuator mechanism with a movable member controlled by two actuators
03/2005
03/31/2005WO2005029502A1 Non-volatile memory and method with bit line to bit line coupled compensation
03/31/2005WO2005029501A1 Boosted substrate/tub programming for flash memories
03/31/2005WO2005029499A2 Low power programming technique for a floating body memory transistor, memory cell, and memory array
03/31/2005WO2005029497A2 Current confined pass layer for magnetic elements utilizing spin-transfer and an mram device using such magnetic elements
03/31/2005WO2005008736A3 1t1c sram
03/31/2005WO2005004162A3 Cross-point mram array with reduced voltage drop across mtj's
03/31/2005WO2005002052A3 Bi-directional buffering for memory data lines
03/31/2005WO2005001807A3 Memory controller and data driver for flat panel display
03/31/2005WO2004102631A3 Reference current generator, and method of programming, adjusting and/or operating same
03/31/2005WO2004082321A3 Multi-channel digital feedback reducer system
03/31/2005US20050071592 Selectable block protection for non-volatile memory
03/31/2005US20050071582 Circuits and methods for providing variable data I/O width for semiconductor memory devices
03/31/2005US20050071543 Memory buffer device integrating refresh
03/31/2005US20050071541 Method and apparatus for implicit DRAM precharge
03/31/2005US20050071540 Memory device with a flexible reduced density option
03/31/2005US20050071116 Temperature sensor scheme
03/31/2005US20050068843 Asynchronous pseudo sram
03/31/2005US20050068840 Methods of selectively activating word line segments enabled by row addresses and semiconductor memory devices having partial activation commands of word line
03/31/2005US20050068838 Semiconductor memory device allowing accurate burn-in test
03/31/2005US20050068837 Asynchronous pseudo SRAM and access method therefor
03/31/2005US20050068834 Magnetic random access memory (MRAM) having a magnetic tunneling junction (MTJ) layer including a tunneling film of uniform thickness and method of manufacturing the same
03/31/2005US20050068833 Input/output line sense amplifiers and/or input/output line drivers in semiconductor memory devices and methods of operating such devices
03/31/2005US20050068832 Semiconductor storage device
03/31/2005US20050068830 Magnetic memory device
03/31/2005US20050068829 Refresh rate adjustment
03/31/2005US20050068828 Merged MOS-bipolar capacitor memory cell
03/31/2005US20050068826 Selective bank refresh
03/31/2005US20050068825 Magnetic memory device and method of manufacturing magnetic memory device
03/31/2005US20050068824 Semiconductor memory
03/31/2005US20050068822 Memory device and its manufacturing method
03/31/2005US20050068816 Semiconductor memory device and method of testing the device
03/31/2005US20050068815 Accelerated life test of mram cells
03/31/2005US20050068813 Circuit for setting one of a plurality of organization forms of an integrated circuit and method for operating it
03/31/2005US20050068811 Non-cascading charge pump circuit and method
03/31/2005US20050068809 Memory
03/31/2005US20050068808 Erase inhibit in non-volatile memories
03/31/2005US20050068807 Semiconductor integrated circuit device
03/31/2005US20050068806 Double density MRAM with planar processing
03/31/2005US20050068803 Method for controlling programming voltage levels of non-volatile memory cells, the method tracking the cell features, and corresponding voltage regulator
03/31/2005US20050068802 Semiconductor storage device and method of controlling the same
03/31/2005US20050068679 Magnetic storage medium and method for making same
03/31/2005US20050068371 Ink jet printhead incorporating a plurality of nozzle arrangement having backflow prevention mechanisms
03/31/2005US20050068275 Driver circuit, as for an OLED display
03/31/2005US20050067645 Semiconductor memory device and method of reading data
03/31/2005DE10339946A1 Semiconductor memory device having a temporary memory for each of one or more memory banks each having several cells for storing data
03/31/2005DE10339894A1 Arrangement for switching a data reader amplifier on and off esp. for a semiconductor memory element with an additional switch for effecting a change in state of control signals
03/31/2005DE102004022576A1 Verfahren und Vorrichtung zum Koppeln von Leitern in einem Magnetspeicher Method and apparatus for coupling of conductors in a magnetic memory
03/30/2005EP1519490A1 Control circuit and reconfigurable logic block
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