Patents
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
03/2005
03/17/2005US20050057279 Input buffer of differential amplification type in semiconductor device
03/17/2005US20050056876 Semiconductor memory device
03/17/2005US20050056869 Nonvolatile semiconductor memory cell matrix, a mehtod for operating the same, monolithic integrated circuits and systems
03/17/2005US20050056866 Circuit arrays having cells with combinations of transistors and nanotube switching elements
03/17/2005US20050056825 Field effect devices having a drain controlled via a nanotube switching element
03/17/2005US20050055829 Method of fabricating a micro-electromechanical fluid ejection device having enhanced actuator strength
03/17/2005DE19848283B4 Halbleiterspeichereinrichtung mit verbessertem Treiber für den Leseverstärker A semiconductor memory device with improved sense amplifier driver for the
03/17/2005DE10361674A1 Nicht-Flüchtiger dynamischer Schreib/Lese-Speicher Non-volatile dynamic read / write memory
03/17/2005DE10336397A1 Memory array for digital data used in e.g. low power-, mobile, ubiquitous-, boot-free computing, employs storage field effect transistors in memory cells
03/17/2005DE102004041023A1 Semiconductor integrated circuit device, has impedance controller to generate control codes that are variably related with impedance of external reference resistor, and termination circuit to terminate transfer line based on codes
03/17/2005DE102004040962A1 Compensating circuit for semiconductor memory, has delay locked loop circuit which receives offset code from up-down counter, and generates pair of clock signals having different phase differences
03/17/2005DE102004031449A1 Gerät und Verfahren zum Kompensieren eines Phasenverzugs in einer Halbleiterspeichervorrichtung Apparatus and method for compensating for a phase delay in a semiconductor memory device
03/17/2005DE102004015575A1 Verfahren, Vorrichtung und System zum Löschen und Schreiben eines magnetischen Direktzugriffsspeichers Method, apparatus and system for erasing and writing a magnetic random access memory
03/17/2005DE102004015555A1 Verfahren zum adaptiven Schreiben eines magnetischen Direktzugriffsspeichers A method for adaptively writing a magnetic random access memory
03/17/2005CA2537632A1 Low voltage operation dram control circuits
03/16/2005EP1514309A1 Deep wordline trench to shield cross coupling between adjacent cells for scaled nand
03/16/2005EP1514276A1 Data storage device
03/16/2005EP1514275A1 Ferroelectric memory with series connected memory cells
03/16/2005EP1514274A1 Memory storage device with heating element
03/16/2005EP1446806B1 A ferroelectric or electret memory circuit
03/16/2005EP1419506B1 Control device for reversing the direction of magnetisation without an external magnetic field
03/16/2005EP1390951B1 Dynamic memory and method for testing a dynamic memory
03/16/2005EP1323167B1 A method for performing write and read operations in a passive matrix memory, and apparatus for performing the method
03/16/2005CN1596474A Circuit for generating a reference voltage having low temperature dependency
03/16/2005CN1596449A Low voltage operation of static random access memory
03/16/2005CN1596448A Folded memory layers
03/16/2005CN1596447A Cascode sense amp and column select circuit and method of operation
03/16/2005CN1595535A Data storage device and a method of reading data in a data storage device
03/16/2005CN1595532A Random-access memory cell/four-transistor random-access memory cell and storing device
03/16/2005CN1595531A 半导体器件 Semiconductor devices
03/16/2005CN1595530A DRAM updated structure capable of changing frequency elastically
03/16/2005CN1595529A 存储器 Memory
03/16/2005CN1595528A 半导体存储装置 The semiconductor memory device
03/16/2005CN1595527A Unified multilevel cell memory
03/16/2005CN1193556C 信号传输装置 Signal transmitting means
03/16/2005CN1193441C Magnetic tunnel device, magnetic storage and element using said device and its access method
03/16/2005CN1193374C 磁存储装置与磁基片 A magnetic storage device and the magnetic substrate
03/15/2005US6868504 Interleaved delay line for phase locked and delay locked loops
03/15/2005US6868474 High performance cost optimized memory
03/15/2005US6868034 Circuits and methods for changing page length in a semiconductor memory device
03/15/2005US6868031 Nonvolatile memory device having circuit for stably supplying desired current during data writing
03/15/2005US6868030 Semiconductor memory apparatus simultaneously accessible via multi-ports
03/15/2005US6868029 Semiconductor device with reduced current consumption in standby state
03/15/2005US6868027 Semiconductor memory device having a DRAM cell structure and handled as a SRAM
03/15/2005US6868026 Semiconductor memory device, and method of controlling the same
03/15/2005US6868025 Temperature compensated RRAM circuit
03/15/2005US6868023 Semiconductor memory device based on dummy-cell method
03/15/2005US6868020 Synchronous semiconductor memory device having a desired-speed test mode
03/15/2005US6868015 Semiconductor memory array of floating gate memory cells with control gate spacer portions
03/15/2005US6868013 Semiconductor memory device
03/15/2005US6868010 Semiconductor memory device having row decoder in which high-voltage-applied portion is located adjacent to low-voltage-applied portion
03/15/2005US6868006 Clock synchronized non-volatile memory device
03/15/2005US6868005 Thin film magnetic memory device provided with magnetic tunnel junctions
03/15/2005US6868004 Thin film magnetic memory device suppressing resistance of transistors present in current path
03/15/2005US6868003 Magnetic random access memory
03/15/2005US6868002 Magnetic memory with reduced write current
03/15/2005US6868001 Semiconductor memory device
03/15/2005US6868000 Coupled body contacts for SOI differential circuits
03/15/2005US6867999 Memory device including a transistor having functions of RAM and ROM
03/15/2005US6867998 Cell array block of FeRAM, and FeRAM using cell array
03/15/2005US6867997 Series feram cell array
03/15/2005US6867994 Semiconductor memory device with memory cells arranged in high density
03/15/2005US6867993 Semiconductor memory device
03/15/2005US6867989 Auto read content addressable memory cell and array
03/15/2005US6867988 Magnetic logic elements
03/15/2005US6867637 Semiconductor integrated circuit device including a substrate bias controller and a current limiting circuit
03/15/2005US6867626 Clock synchronization circuit having bidirectional delay circuit strings and controllable pre and post stage delay circuits connected thereto and semiconductor device manufactured thereof
03/15/2005US6867468 Magnetic shielding for reducing magnetic interference
03/15/2005US6867445 Semiconductor memory devices including different thickness dielectric layers for the cell transistors and refresh transistors thereof
03/15/2005US6867131 Apparatus and method of increasing sram cell capacitance with metal fill
03/15/2005US6866789 Method of manufacture of a gear driven shutter ink jet printer
03/10/2005WO2005022653A2 Magnetoresistive random access memory with reduced switching field variation
03/10/2005WO2005022549A1 A polymer memory having a ferroelectric polymer memory material with cell sizes that are asymmetric
03/10/2005WO2005022548A1 Reliable ferro fuse cell
03/10/2005WO2005022547A1 Resistance cross-point array reader
03/10/2005WO2005022546A1 Active shielding for a circuit comprising magnetically sensitive materials
03/10/2005WO2005022545A1 Mram array with segmented magnetic write lines
03/10/2005WO2005022544A1 Method and system for controlling write current in magnetic memory
03/10/2005WO2005022543A1 Method and system for controlling write current in magnetic memory
03/10/2005WO2005022541A1 Controlled substrate voltage for memory switches
03/10/2005WO2004112040A3 Methods of increasing the reliability of a flash memory
03/10/2005WO2004100216B1 A non-volatile memory having a bias on the source electrode for hci programming
03/10/2005WO2003090229A3 Memory cells enhanced for resistance to single event upset
03/10/2005US20050055621 Magnetic memory with error correction coding
03/10/2005US20050055491 Method and apparatus for data inversion in memory device
03/10/2005US20050055170 Data storage device and a method of reading data in a data storage device
03/10/2005US20050054166 Conductive metal oxide gate ferroelectric memory transistor
03/10/2005US20050054138 Method of fabricating trench isolated cross-point memory array
03/10/2005US20050052944 Semiconductor integrated circuit device
03/10/2005US20050052943 Memory device and method of reading data from a memory device
03/10/2005US20050052942 Trench isolated cross-point memory array
03/10/2005US20050052941 Semiconductor memory
03/10/2005US20050052938 Magnetic memory device and method of manufacturing the same
03/10/2005US20050052935 Semiconductor integrated circuit
03/10/2005US20050052934 Unified multilevel cell memory
03/10/2005US20050052933 [device and method for breaking leakage current path]
03/10/2005US20050052931 Sense amplifier power-gating technique for integrated circuit memory devices and those devices incorporating embedded dynamic random access memory (DRAM)
03/10/2005US20050052929 Thin film magnetic memory device suppressing internal magnetic noises
03/10/2005US20050052928 Semiconductor memory device and method for manufacturing same
03/10/2005US20050052925 Semiconductor memory device and semiconductor integrated circuit device