Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
03/2005
03/01/2005US6862230 Efficient column redundancy techniques
03/01/2005US6862229 Physically alternating sense amplifier activation
03/01/2005US6862228 High reliable reference current generator for MRAM
03/01/2005US6862227 Semiconductor memory device having the operating voltage of the memory cell controlled
03/01/2005US6862223 Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
03/01/2005US6862219 Weak programming method of non-volatile memory
03/01/2005US6862218 Multi-state memory
03/01/2005US6862215 MRAM data line configuration and method of operation
03/01/2005US6862214 Phase change memory array
03/01/2005US6862213 Semiconductor memory device and control method thereof
03/01/2005US6862212 Multi-bit magnetic memory cells
03/01/2005US6862211 Magneto-resistive memory device
03/01/2005US6862210 Magnetic random access memory for storing information utilizing magneto-resistive effects
03/01/2005US6862209 Thin film magnetic memory device with magnetic tunnel junction
03/01/2005US6862208 Memory device with sense amplifier and self-timed latch
03/01/2005US6862207 Static random access memory
03/01/2005US6862206 Memory module hybridizing an atomic resolution storage (ARS) memory and a magnetic memory
03/01/2005US6862205 Semiconductor memory device
03/01/2005US6862204 Semiconductor integrated circuit having connecting wires for interconnecting bit lines
03/01/2005US6861752 Semiconductor device having wiring line with hole, and manufacturing method thereof
03/01/2005US6861708 Semiconductor memory device having a low potential body section
03/01/2005US6861707 Negative differential resistance (NDR) memory cell with reduced soft error rate
03/01/2005US6861687 Electrically programmable resistance cross point memory structure
03/01/2005US6861314 Semiconductor memory device utilizing tunnel magneto resistive effects and method for manufacturing the same
02/2005
02/24/2005WO2005017953A2 In situ patterning of electrolyte for molecular information storage devices
02/24/2005WO2005017914A1 Semiconductor memory and operation method of semiconductor memory
02/24/2005WO2004051666A3 Reducing effects of noise coupling in integrated circuits with memory arrays
02/24/2005WO2004021359A3 Software refreshed memory device and method
02/24/2005WO2004001801A3 Insulated-gate semiconductor device and approach involving junction-induced intermediate region
02/24/2005WO2003100786A8 Serially sensing the output of multilevel cell arrays
02/24/2005WO2003077256A3 Programmable conductor random access memory and method for sensing same
02/24/2005US20050044441 Memory device for compensating for a clock skew causing a centering error and a method of compensating for the clock skew
02/24/2005US20050044305 Semiconductor memory module
02/24/2005US20050044302 Non-standard dual in-line memory modules with more than two ranks of memory per module and multiple serial-presence-detect devices to simulate multiple modules
02/24/2005US20050042827 Method of manufacturing semiconductor integrated circuit device having capacitor element
02/24/2005US20050042825 Image displaying method and image displaying device
02/24/2005US20050042776 Method of producing an integrated circuit arrangement with field-shaping electrical conductor
02/24/2005US20050041520 Semiconductor memory device
02/24/2005US20050041519 Integrated clock supply chip for a memory module, memory module comprising the integrated clock supply chip, and method for operating the memory module under test conditions
02/24/2005US20050041517 Sensing the state of a storage cell including a magnetic element
02/24/2005US20050041514 Low-power consumption semiconductor memory device
02/24/2005US20050041513 Multi-level semiconductor memory architecture and method of forming the same
02/24/2005US20050041512 Hybrid open and folded digit line architecture
02/24/2005US20050041508 Current limiting antifuse programming path
02/24/2005US20050041507 Fuse circuit
02/24/2005US20050041506 System and method for performing partial array self-refresh operation in a semiconductor memory device
02/24/2005US20050041502 Circuit and method for evaluating and controlling a refresh rate of memory cells of a dynamic memory
02/24/2005US20050041501 Memory device having a configurable oscillator for refresh operation
02/24/2005US20050041500 Dynamic random access memory devices and method of controlling refresh operation thereof
02/24/2005US20050041499 Semiconductor device and semiconductor memory device
02/24/2005US20050041498 Writing circuit for a phase change memory device
02/24/2005US20050041494 High density non-volatile memory device
02/24/2005US20050041493 Semiconductor storage device
02/24/2005US20050041483 Apparatus and method of compensating for phase delay in semiconductor device
02/24/2005US20050041480 Method for transparent updates of output driver impedance
02/24/2005US20050041470 Nonvolatile random access memory and method of fabricating the same
02/24/2005US20050041467 Chalcogenide memory
02/24/2005US20050041463 Mram layer having domain wall traps
02/24/2005US20050041462 High speed low power magnetic devices based on current induced spin-momentum transfer
02/24/2005US20050041461 Static semiconductor storage device
02/24/2005US20050041459 Interface for removable storage devices
02/24/2005US20050041457 Single transistor vertical memory gain cell
02/24/2005US20050041456 Magneto-resistive effect element and magnetic memory
02/24/2005US20050041452 Circuit and method for reducing fatigue in ferroelectric memories
02/24/2005US20050041451 Multimode data buffer and method for controlling propagation delay time
02/24/2005US20050041449 Asymmetric static random access memory device having reduced bit line leakage
02/24/2005US20050041086 Pagewidth printer that includes a computer-connectable keyboard
02/24/2005US20050040883 Semiconductor integrated circuit device
02/24/2005US20050040845 Semiconductor integrated circuit device capable of controlling impedance
02/24/2005US20050040844 Apparatus and method of error detection and correction in a radiation-hardened static random access memory field- programmable gate array
02/24/2005US20050040804 Plate voltage generation circuit capable controlling dead band
02/24/2005US20050040803 Circuit for generating a reference voltage having low temperature dependency
02/24/2005US20050040546 Radiation hardened microelectronic device
02/24/2005US20050040447 Magnetic memory device having a plurality of magneto-resistance effect elements arranged in a matrix form and method for manufacturing the same
02/24/2005US20050040433 Magnetic memory with spin-polarized current writing, using amorphous ferromagnetic alloys, writing method for same
02/24/2005DE10333522A1 Speicheranordnung zur Verarbeitung von Daten und Verfahren Memory means for processing data and methods
02/24/2005DE102004036893A1 Semiconductor memory device e.g. synchronous dynamic RAM outputs data synchronized with input clock signal and preamble representing start of data, on receiving data read command with clock signal
02/24/2005DE102004034184A1 Ein System von multiplexierten Datenleitungen in einem dynamischen Direktzugriffsspeicher A system of multiplexed data lines in a dynamic random access memory
02/24/2005DE102004033443A1 Flashspeicherbauelement mit Mehrpegelzelle sowie Lese- und Programmierverfahren Flash memory device with multi-level cell and literacy programming method
02/24/2005DE102004026000A1 Cell field for DRAMs comprises memory cells having lower source/drain regions with sections of trenched source/drain layer perforated by perforated trenches and word line trenches
02/24/2005DE10063732B4 Halbleiterspeicherbauelement mit hierarchischer Wortleitungsstruktur Semiconductor memory device with a hierarchical word line structure
02/24/2005DE10061604B4 Halbleiterspeicher, der mit einem Reihenadressendecodierer versehen ist, der eine reduzierte Signalausbreitungsverzögerungszeit hat A semiconductor memory, which is provided with a row address decoder, which has a reduced signal propagation delay time
02/23/2005EP1508901A1 Memory circuit having nonvolatile identification memory and associated process
02/23/2005EP1508128A1 System and method of authentifying
02/23/2005EP1508085A1 Methods of factoring and modular arithmetic
02/23/2005CN1586007A Memory device
02/23/2005CN1585986A A biasing technique for a high density sram
02/23/2005CN1585985A Semiconductor storage device
02/23/2005CN1585124A Fuse circuit
02/23/2005CN1190849C Semiconductor memory unit and array using ultra-thin medium breakdown phenomenon
02/23/2005CN1190796C Integrated memory with reference of electric potential and operation method of such memory
02/22/2005US6859857 Memory interface circuit
02/22/2005US6859415 Fully-hidden refresh dynamic random access memory
02/22/2005US6859414 Data input device in semiconductor memory device
02/22/2005US6859413 Method and apparatus for DLL lock latency detection
02/22/2005US6859412 Circuit for controlling driver strengths of data and data strobe in semiconductor device
02/22/2005US6859411 Circuit and method for writing and reading data from a dynamic memory circuit
02/22/2005US6859409 Semiconductor memory having sense amplifier architecture
02/22/2005US6859408 Current limiting antifuse programming path
02/22/2005US6859407 Memory with auto refresh to designated banks
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