Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
05/2014
05/06/2014US8717811 Latching circuit
05/06/2014US8717810 Phase change memory device and computing system having the same
05/06/2014US8717809 Phase change memory programming method and phase change memory
05/06/2014US8717808 Magnetic devices and structures
05/06/2014US8717807 Independently-controlled-gate SRAM
05/06/2014US8717806 Storage element, storage device, signal processing circuit, and method for driving storage element
05/06/2014US8717805 Nonvolatile RAM
05/06/2014US8717804 Three dimensional programmable resistance memory device with a read/write circuit stacked under a memory cell array
05/06/2014US8717803 Metal-insulator-metal-insulator-metal (MIMIM) memory device
05/06/2014US8717802 Reconfigurable multi-level sensing scheme for semiconductor memories
05/06/2014US8717801 Semiconductor memory device
05/06/2014US8717800 Method and apparatus pertaining to a ferroelectric random access memory
05/06/2014US8717797 Semiconductor memory device with hierarchical bitlines
05/06/2014US8716818 Magnetoresistive element and method of manufacturing the same
05/01/2014WO2014066586A1 Bipolar logic gates on mos-based memory chips
05/01/2014WO2014066484A1 An adaptive reference scheme for magnetic memory applications
05/01/2014WO2014066402A1 Circuit and layout design methods and logic cells for soft error hard integrated circuits
05/01/2014WO2014066263A1 Dynamic bit line bias for programming non-volatile memory
05/01/2014WO2014065775A1 Performing refresh of a memory device in response to access of data
05/01/2014WO2014065774A1 Refreshing a group of memory cells in response to presence of potential disturbance
05/01/2014WO2014065049A1 Magnetic-domain-wall-displacement memory cell and initializing method therefor
05/01/2014WO2014063939A1 Thermally assisted mram cell and method for writing a plurality of bits in the mram cell
05/01/2014WO2014063938A1 Self-referenced mram element and device having improved magnetic field
05/01/2014WO2013191958A3 Memory cells, semiconductor device structures, memory systems, and methods of fabrication
05/01/2014US20140119142 Semiconductor integrated circuit
05/01/2014US20140119137 Method and apparatus for dynamically adjusting voltage reference to optimize an i/o system
05/01/2014US20140119133 Clock signal generators having a reduced power feedback clock path and methods for generating clocks
05/01/2014US20140119111 Magnetic memory including magnetic nanowire and write method therein
05/01/2014US20140119109 Magnetoresistive element, magnetic memory, and method of manufacturing magnetoresistive element
05/01/2014US20140119108 Memory system including nonvolatile memory and method of operating nonvolatile memory
05/01/2014US20140119107 Magnetic memory device having bidirectional read scheme
05/01/2014US20140119106 Magnetic memory devices and methods of operating the same
05/01/2014US20140119105 Adaptive Reference Scheme for Magnetic Memory Applications
05/01/2014US20140119104 Data-Aware SRAM Systems and Methods Forming Same
05/01/2014US20140119103 SRAM Cells Suitable for Fin Field-Effect Transistor (FinFET) Process
05/01/2014US20140119102 Dummy read to prevent crowbar current during read-write collisions in memory arrays with crosscoupled keepers
05/01/2014US20140119100 Sram with improved write operation
05/01/2014US20140119099 Dram-type device with low variation transistor peripheral circuits, and related methods
05/01/2014US20140119092 Programmable lsi
05/01/2014US20140119091 Bit-line sense amplifier, semiconductor memory device and memory system including the same
04/2014
04/30/2014EP2725580A1 Thermally assisted MRAM cell and method for writing a plurality of bits in the MRAM cell
04/30/2014EP2725579A1 TA-MRAM cell with seed layer having improved data retention, reduced writing and reading fields
04/30/2014EP2724344A1 Spin-torque transfer magnetic memory cell structures with symmetric switching and single direction current programming
04/30/2014EP2724342A1 Short circuit reduction in a ferroelectric memory cell comprising a stack of layers arranged on a flexible substrate
04/30/2014DE102007059547B4 Elektrische Schaltung und Verfahren zum Betreiben einer elektrischen Schaltung Electrical circuit and method for operating an electrical circuit
04/30/2014CN203573659U Static random access memory with automatic bias
04/30/2014CN103765519A Intelligent shifting of read pass voltages for non-volatile storage
04/30/2014CN102339636B Semiconductor memory device and method of driving the same
04/30/2014CN101783166B Nonvolatile magnetic memory device
04/30/2014CN101310343B Memory diagnosis device
04/29/2014US8713404 Controller interface providing improved data reliability
04/29/2014US8711650 Semiconductor device including multi-chip
04/29/2014US8711646 Architecture, system and method for testing resistive type memory
04/29/2014US8711645 Victim port-based design for test area overhead reduction in multiport latch-based memories
04/29/2014US8711635 Nonvolatile semiconductor memory device
04/29/2014US8711632 Semiconductor memory device
04/29/2014US8711631 Management of memory array with magnetic random access memory (MRAM)
04/29/2014US8711628 Use of emerging non-volatile memory elements with flash memory
04/29/2014US8711624 Memory device and self interleaving method thereof
04/29/2014US8711621 Flash multi-level threshold distribution scheme
04/29/2014US8711620 Memory device having collaborative filtering to reduce noise
04/29/2014US8711617 Data modulation for groups of memory cells
04/29/2014US8711616 Single check memory devices and methods
04/29/2014US8711615 Memory kink checking
04/29/2014US8711614 Memory elements with increased write margin and soft error upset immunity
04/29/2014US8711613 Non-volatile flash-RAM memory with magnetic memory
04/29/2014US8711611 Supply voltage generating circuit and semiconductor device having the same
04/29/2014US8711610 Non-volatile memory array and device using erase markers
04/29/2014US8711609 Nonvolatile memory device
04/29/2014US8711608 Memory with separate read and write paths
04/29/2014US8711607 Semiconductor device
04/29/2014US8711606 Data security for dynamic random access memory using body bias to clear data at power-up
04/29/2014US8711605 Resistive memory element sensing using averaging
04/29/2014US8711604 Non-volatile semiconductor memory and data processing method in non-volatile semiconductor memory
04/29/2014US8711603 Permutational memory cells
04/29/2014US8711602 Semiconductor memory device
04/29/2014US8711601 Resistive random access memory cell and resistive random access memory module
04/29/2014US8711600 High density molecular memory storage with read and write capabilities
04/29/2014US8711599 Polarization-coupled ferroelectric unipolar junction memory and energy storage device
04/29/2014US8711596 Memory system with data line switching scheme
04/29/2014US8710604 Magnetoresistive element and manufacturing method of the same
04/24/2014WO2014062681A1 Inverted orthogonal spin transfer layer stack
04/24/2014WO2014062634A1 Increased magnetoresistance in an inverted orthogonal spin transfer layer stack
04/24/2014WO2014062558A1 Systems and methods for reading resistive random access memory (rram) cells
04/24/2014WO2014062435A1 Non-volatile memory array and method of using same for fractional word programming
04/24/2014US20140115383 Multiple level cell memory device with single bit per cell, re-mappable memory block
04/24/2014US20140115248 Device, system, and method of memory allocation
04/24/2014US20140115247 Information recording device and information recording method
04/24/2014US20140112086 Refresh method, refresh address generator, volatile memory device including the same
04/24/2014US20140112084 On-Die Termination of Address and Command Signals
04/24/2014US20140112067 Apparatus, Storage Device, Switch and Methods, Which Include Microstructures Extending from a Support
04/24/2014US20140112066 Circuit Arrangement and Method of Forming the Same
04/24/2014US20140112065 Semiconductor memory device
04/24/2014US20140112064 Sram global precharge, discharge, and sense
04/24/2014US20140112063 Implementing sdram having no ras to cas delay in write operation
04/24/2014US20140112062 Method and system for an adaptive negative-boost write assist circuit for memory architectures
04/24/2014US20140112060 Sram global precharge, discharge, and sense
04/24/2014US20140112052 Memory Programming Methods And Memory Systems
04/24/2014US20140112045 Memory system incorporating a circuit to generate a delay signal and an associated method of operating a memory system
04/24/2014US20140110660 Nonvolatile memory cell without a dielectric antifuse having high- and low-impedance states
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