Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
03/2014
03/11/2014US8670269 Resistive memory device and method of writing data using multi-mode switching current
03/11/2014US8670268 Magnetoresistive element and magnetic memory using the same
03/11/2014US8670267 Data storage methods and devices
03/11/2014US8670266 Non-volatile flip-flop
03/11/2014US8670265 Reducing power in SRAM using supply voltage control
03/11/2014US8670264 Multi-port magnetic random access memory (MRAM)
03/11/2014US8670263 Data holding device
03/06/2014WO2014036101A1 Metal protection layer over sin encapsulation for spin-torque mram device applications
03/06/2014WO2014035874A1 Diode segmentation in memory
03/06/2014WO2014035553A1 Direct multi-level cell programming
03/06/2014WO2014034559A1 Fbc memory or thyristor memory for refreshing unused word line
03/06/2014WO2014034084A1 Semiconductor device
03/06/2014US20140068172 Selective refresh with software components
03/06/2014US20140064009 Memory device
03/06/2014US20140063997 Dram refresh
03/06/2014US20140063976 Non-volatile semiconductor memory device adapted to store a multi-valued data in a single memory cell
03/06/2014US20140063935 Semiconductor memory device having vertical channels, memory system having the same, and method of fabricating the same
03/06/2014US20140063934 Semiconductor device having buried gate, method of fabricating the same, and module and system having the same
03/06/2014US20140063933 Asymmetric write scheme for magnetic bit cell elements
03/06/2014US20140063924 Nonvolatile semiconductor memory device and operating method of the same
03/06/2014US20140063923 Mismatch Error Reduction Method and System for STT MRAM
03/06/2014US20140063922 Mram word line power control scheme
03/06/2014US20140063921 Method and system for providing inverted dual magnetic tunneling junction elements
03/06/2014US20140063920 Static random access memory that initializes to pre-determined state
03/06/2014US20140063918 Control circuit of sram and operating method thereof
03/06/2014US20140063917 Read self-time technique with fine grained programmable logic delay element
03/06/2014US20140063916 Sram local evaluation logic for column selection
03/06/2014US20140063915 Differential vector storage for dynamic random access memory
03/06/2014US20140063909 Nonvolatile memory element, nonvolatile memory device, and writing method for use in nonvolatile memory element
03/06/2014US20140063905 Semiconductor memory device capable of measuring write current and method for measuring write current
03/06/2014US20140063903 Resistive random access memory, controlling method and manufacturing method therefor
03/06/2014US20140063902 Memory devices, circuits and, methods that apply different electrical conditions in access operations
03/06/2014US20140063901 Memory devices, circuits and, methods that apply different electrical conditions in access operations
03/06/2014US20140063900 Apparatus and method for detecting reflow process
03/06/2014US20140063899 Methods, devices and systems using over-reset state in a memory cell
03/06/2014US20140063898 Systems, methods and devices for programming a multilevel resistive memory cell
03/06/2014US20140063897 Non-volatile memory including reference signal path
03/06/2014US20140063896 Nonvolatile memory apparatus and method for driving the same
03/06/2014US20140063892 Diode segmentation in memory
03/06/2014US20140063891 Semiconductor memory device
03/06/2014US20140063888 Memory array plane select and methods
03/06/2014US20140062530 Switching mechanism of magnetic storage cell and logic unit using current induced domain wall motions
03/06/2014DE102013109327A1 Speichervorrichtung zum Verringern eines Schreibfehlers, ein System mit derselben und Verfahren davon Memory means for reducing a clerical error, a system with the same and method thereof
03/06/2014DE102013014354A1 Verfahren und System zur Reduzierung eines Nichtübereinstimmungsfehlers für ein STT-MRAM A method and system for reducing a mismatch error for a STT-MRAM
03/05/2014EP2704012A1 Adaptive error correction for non-volatile memories
03/05/2014CN203465950U Memory comparison and refresh circuit module
03/05/2014CN103620687A Semiconductor storage device
03/05/2014CN103620685A Sensing circuit
03/05/2014CN103620684A Sensing circuit
03/05/2014CN103620681A Short circuit reduction in an electronic component comprising a stack of layers arranged on a flexible substrate
03/05/2014CN103617808A Reading and caching circuit and method of SRAM (Static Random Access Memory)
03/05/2014CN103616946A Video playing control device and method
03/05/2014CN101809670B Information processor, storage section control device, and storage section control method
03/04/2014US8665652 Method for erasing memory array
03/04/2014US8665651 Reference cell circuit and method of producing a reference current
03/04/2014US8665648 Flash memory device having seed selector circuit
03/04/2014US8665647 Nonvolatile memory device, memory system, and read method thereof
03/04/2014US8665645 Drift compensation in a flash memory
03/04/2014US8665644 Stacked memory device and method of fabricating same
03/04/2014US8665642 Pattern-sensitive coding of data for storage in multi-level memory cells
03/04/2014US8665641 Semiconductor device
03/04/2014US8665640 Spin torque transfer cell structure utilizing field-induced antiferromagnetic or ferromagnetic coupling
03/04/2014US8665639 Magnetoresistive element and magnetic memory
03/04/2014US8665638 MRAM sensing with magnetically annealed reference cell
03/04/2014US8665637 Semiconductor memory
03/04/2014US8665636 Semiconductor storage device
03/04/2014US8665635 Memory cell
03/04/2014US8665634 Semiconductor memory device
03/04/2014US8665633 Nonvolatile variable resistance memory element writing method, and nonvolatile variable resistance memory device
03/04/2014US8665632 Semiconductor memory device
03/04/2014US8665631 Resistive random memory cell and memory
03/04/2014US8665630 Memory cell operation including capacitance
03/04/2014US8665629 Condensed memory cell structure using a FinFET
03/04/2014US8665628 Ferroelectric memory device
03/04/2014US8664632 Memory device
02/2014
02/27/2014WO2014031444A1 Mtp mtj device
02/27/2014WO2014031442A1 Multi-level memory cell using multiple magentic tunnel junctions with varying mgo thickness
02/27/2014WO2014031366A1 Read threshold estimation in analog memory cells using simultaneous multi-voltage sense
02/27/2014WO2014030941A1 Apparatus and method for data movement
02/27/2014WO2014030758A1 Semiconductor device preventing multiword state
02/27/2014US20140059287 Row hammer refresh command
02/27/2014US20140059282 Hybrid nanotube/cmos dynamically reconfigurable architecture and system therefore
02/27/2014US20140056094 Word-line activation circuit, semiconductor memory device, and semiconductor integrated circuit
02/27/2014US20140056077 Compensating for off-current in a memory
02/27/2014US20140056061 Method and system for providing dual magnetic tunneling junctions using spin-orbit interaction-based switching and memories utilizing the dual magnetic tunneling junctions
02/27/2014US20140056060 Method and system for providing a magnetic tunneling junction using spin-orbit interaction based switching and memories utilizing the magnetic tunneling junction
02/27/2014US20140056059 Symmetrical Differential Sensing Method and System for STT MRAM
02/27/2014US20140056058 Differential Sensing Method and System for STT MRAM
02/27/2014US20140056057 Semiconductor memory device and method for controlling semiconductor memory device
02/27/2014US20140056054 Resistive memory device and programming method thereof
02/27/2014US20140056053 Unipolar memory devices
02/27/2014DE102013217051A1 Speicherzelle und Speicher Memory cell and memory
02/27/2014DE102013013928A1 Symmetrisches differentielles Leseverfahren und Lesesystem für ein STT-MRAM Balanced differential reading method and reading system for a STT-MRAM
02/27/2014DE102013013926A1 Differentielles Leseverfahren und Lesesystem für ein STT-MRAM Differential reading process and reading system for a STT-MRAM
02/27/2014DE102011014587B4 Schneller Austritt aus Selbstauffrischungszustand eines Speichergeräts Faster exit from self-refresh state of a storage device
02/26/2014CN203456097U Static random access memory unit
02/26/2014CN102376352B Read-write control system and method of SDRAM (synchronous dynamic random access memory) dual-port image data based on FPGA (field programmable gate array)
02/26/2014CN102150213B Circuit and method for optimizing memory sense amplifier timing
02/25/2014US8661318 Memory management in a non-volatile solid state memory device
02/25/2014US8661285 Dynamically calibrated DDR memory controller
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