Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
03/2014
03/19/2014CN103646665A I/O (Input/Output) interface circuit of asynchronous SRAM (Static Random Access Memory)
03/19/2014CN103646663A Memory array and method of equilibrating digit lines in memory array
03/19/2014CN102306501B Programming defferently sized margins and sensing with compensations at select states for improved read operations in non-volatile memory
03/19/2014CN102254569B Quad-data rate (QDR) controller and realization method thereof
03/19/2014CN102024489B Semiconductor memory device and multilayered chip semiconductor device
03/18/2014US8675423 Apparatuses and methods including supply current in memory
03/18/2014US8675417 Method and system for adaptive coding in flash memories
03/18/2014US8675415 Nonvolatile memory device having selectable sensing modes, memory system having the same and programming method thereof
03/18/2014US8675414 Group based read reference voltage management in flash memory
03/18/2014US8675413 Reference current sources
03/18/2014US8675411 Background power consumption reduction of electronic devices
03/18/2014US8675410 Hierarchical common source line structure in NAND flash memory
03/18/2014US8675409 Non-volatile memory devices
03/18/2014US8675405 Method to reduce program disturbs in non-volatile memory cells
03/18/2014US8675403 Gated diode memory cells
03/18/2014US8675402 Nonvolatile memory cell, nonvolatile memory device and method for driving the same
03/18/2014US8675401 Spin-transfer torque memory self-reference read method
03/18/2014US8675400 Magnetic memory
03/18/2014US8675399 Magnetic unit and magnetic storage device
03/18/2014US8675398 Volatile memory elements with soft error upset immunity
03/18/2014US8675397 Cell structure for dual-port SRAM
03/18/2014US8675396 Integrated circuit devices and systems having programmable impedance elements with different response types
03/18/2014US8675395 Low noise memory array
03/18/2014US8675394 Semiconductor memory device with oxide semiconductor transistor
03/18/2014US8675393 Method for driving non-volatile memory element, and non-volatile memory device
03/18/2014US8675392 Methods of reading and using memory cells
03/18/2014US8675391 Refreshing memristive systems
03/18/2014US8675390 System and method for MRAM having controlled averagable and isolatable voltage reference
03/18/2014US8675389 Memory element with a reactive metal layer
03/18/2014US8675388 Nonvolatile semiconductor memory device
03/18/2014US8675387 Variable resistance nonvolatile memory device and programming method for same
03/18/2014US8675386 Memory device having resistance unit
03/18/2014US8674724 Field programmable gate array utilizing two-terminal non-volatile memory
03/13/2014WO2014039571A1 Mram word line power control scheme
03/13/2014WO2014039459A1 Non-volatile storage with joint hard bit and soft bit reading
03/13/2014WO2014039164A1 On chip dynamic read level scan and error detection for non-volatile storage
03/13/2014WO2014039129A1 Write data preservation for non-volatile storage
03/13/2014WO2014038341A1 Nonvolatile content addressable memory
03/13/2014WO2014038340A1 Nonvolatile content addressable memory and method for operating same
03/13/2014WO2014037116A1 Differential vector storage for dynamic random access memory
03/13/2014US20140071778 Memory device refresh
03/13/2014US20140071754 Semiconductor memory device for storing multivalued data
03/13/2014US20140071745 Magnetoresistive memory device
03/13/2014US20140071744 Nonvolatile memory module, memory system including nonvolatile memory module, and controlling method of nonvolatile memory module
03/13/2014US20140071743 Memory system including nonvolatile memory device and control method thereof
03/13/2014US20140071742 Semiconductor memory device and method of operating the same
03/13/2014US20140071741 Otp cell with reversed mtj connection
03/13/2014US20140071740 Otp scheme with multiple magnetic tunnel junction devices in a cell
03/13/2014US20140071739 Reference level adjustment scheme
03/13/2014US20140071738 Reference cell repair scheme
03/13/2014US20140071737 Local write and read assist circuitry for memory device
03/13/2014US20140071736 Testing signal development on a bit line in an sram
03/13/2014US20140071735 Initializing dummy bits of an sram tracking circuit
03/13/2014US20140071733 Multi-port memory devices and methods having programmable impedance elements
03/13/2014US20140071732 Nonvolatile magneto-electric random access memory circuit with burst writing and back-to-back reads
03/13/2014DE19927878B4 Halbleiterspeicherbauelement mit Adressendecoder und Adressendecodierverfahren hierfür Semiconductor memory device with address decoder and address decoding method therefor
03/13/2014DE102006032438B4 Halbleiterspeichervorrichtung mit verbundenen Bitleitungen sowie Datenverschiebungsverfahren hierfür A semiconductor memory device with bit lines and associated data shift method therefor
03/13/2014DE102005035079B4 Speichersystem, synchrones Speicherbauelement und Betriebsverfahren Storage system, synchronous memory device and method of operation
03/13/2014DE10015370B4 Halbleiterspeicherbauelement mit aktivierbaren und deaktivierbaren Wortleitungen Semiconductor memory device with and deactuable word lines
03/12/2014CN103633240A Magnetic devices having perpendicular magnetic tunnel junction
03/12/2014CN103633239A Megnetic memory and providing method and programming method
03/12/2014CN103632722A Memory system, program method thereof, and computing system including the same
03/12/2014CN103632717A Digital static CMOS (Complementary Metal-Oxide-Semiconductor Transistor) element
03/12/2014CN103632716A Semiconductor memory device and method for controlling semiconductor memory device
03/12/2014CN103632715A Two-module redundancy configuration memory unit circuit used in programmable logic device
03/12/2014CN103632714A Decoding circuit for reducing FPGA configuration memory bit number
03/12/2014CN103632713A Static random access memory and improving method for storage performance thereof
03/12/2014CN103632712A Memory cell and memory
03/12/2014CN103632711A Single-event latch-up prevention techniques for a semiconductor device
03/12/2014CN103632710A Semiconductor memory device
03/12/2014CN103632709A Semiconductor memory device
03/12/2014CN103632708A Self-refreshing control device and method for synchronous dynamic random access memory
03/12/2014CN103632707A Symmetrical differential sensing method and system for STT MRAM
03/12/2014CN103632706A Differential sensing method and system for STT MRAM
03/12/2014CN102751244B Semiconductor device and forming method of semiconductor device as well as radio frequency identification chip and forming method of radio frequency identification chip
03/12/2014CN102568564B Combined SET (Single-Electron Transistor)/CMOS (Complementary Metal-Oxide Semiconductor) static storage unit based on NDR (Negative Differential Resistance) property
03/12/2014CN102456395B Electronic pump for low-supply voltage
03/12/2014CN102446541B Magnetic random access memory and manufacturing method thereof
03/12/2014CN102376350B Variation-tolerant word-line under-drive scheme for random access memory
03/12/2014CN102376347B Controller for high-speed read-write interface
03/12/2014CN102150216B Multi-pass programming for memory with reduced data storage requirement
03/12/2014CN102067233B Nonvolatile memory and method with index programming and reduced verify
03/12/2014CN102054524B Information storage element and method for driving same
03/12/2014CN101978426B Magnetically de-coupling magnetic memory cells and bit/word lines for reducing bit selection errors
03/12/2014CN101930791B Memory and data processing method
03/12/2014CN101923889B Memory device and memory
03/12/2014CN101573763B Programming NAND flash memory with reduced program disturb
03/12/2014CN101546990B Programmable input/output structure and method for implementing bi-directional data bus
03/11/2014US8671293 Multi-core system energy consumption optimization
03/11/2014US8671239 Nonvolatile memory apparatus for performing wear-leveling and method for controlling the same
03/11/2014US8670282 Redundancy circuits and operating methods thereof
03/11/2014US8670279 Non-volatile memory device and program method thereof
03/11/2014US8670278 Method and apparatus for extending the lifetime of a non-volatile trapped-charge memory
03/11/2014US8670276 Host-managed logical mass storage device using magnetic random access memory (MRAM)
03/11/2014US8670275 Memory with sub-blocks
03/11/2014US8670274 Data storage in analog memory cells using modified pass voltages
03/11/2014US8670273 Methods for program verifying a memory cell and memory devices configured to perform the same
03/11/2014US8670272 Memory with weighted multi-page read
03/11/2014US8670271 Magnetic stack having assist layers
03/11/2014US8670270 Method of operating phase-change memory
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