| Patents for G06F 5 - Methods or arrangements for data conversion without changing the order or content of the data handled (8,116) |
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| 07/03/1991 | EP0435802A2 Method of decompressing compressed data |
| 07/03/1991 | EP0435383A2 Circuit for bit adaptation |
| 06/26/1991 | EP0434381A2 Difference comparison between two asynchronous pointers and a programmable value |
| 06/26/1991 | EP0433520A1 Elastic configurable buffer for buffering asynchronous data |
| 06/25/1991 | US5027351 Asynchronous time division communication system |
| 06/25/1991 | US5027330 FIFO memory arrangement including a memory location fill indication |
| 06/25/1991 | US5027326 Self-timed sequential access multiport memory |
| 06/25/1991 | US5027300 Two level multiplexer circuit shifter apparatus |
| 06/19/1991 | EP0433071A2 Method and apparatus for management of non-uniform data |
| 06/18/1991 | CA1285075C Dual byte order computer architecture |
| 06/05/1991 | EP0430051A2 Byte wide elasticity buffer |
| 06/05/1991 | EP0429786A2 Data synchronizing buffer |
| 06/04/1991 | US5021994 Look-ahead flag generator |
| 06/04/1991 | US5021986 Total sum calculation circuit capable of rapidly calculating a total sum of more than two input data represented by a floating point representation |
| 06/02/1991 | CA2029784A1 Byte wide elasticity buffer |
| 05/29/1991 | EP0429306A2 Data compaction system |
| 05/29/1991 | EP0429305A2 Data processing system including a plurality of data processing devices operating in parallel |
| 05/29/1991 | EP0428771A1 Bidirectional data transfer device |
| 05/28/1991 | US5020013 Bidirectional variable bit shifter |
| 05/18/1991 | WO1991007830A1 Clock dejitter circuits for regenerating jittered clock signals |
| 05/14/1991 | US5016221 First-in, first-out (FIFO) memory with variable commit point |
| 05/08/1991 | EP0426156A2 Floppy disk controller with DMA verify operations |
| 05/08/1991 | EP0425990A2 Cell exchanging apparatus |
| 05/08/1991 | EP0425964A2 Asynchronous voice reconstruction for a digital communication system |
| 05/08/1991 | EP0425764A2 Input data control system and data management apparatus for use therewith |
| 05/07/1991 | US5014235 Convolution memory |
| 05/04/1991 | CA2028378A1 Floppy disk controller with dma verify operations |
| 05/02/1991 | EP0424407A1 Intermediate spreadsheet structure. |
| 05/01/1991 | CA2021266A1 Input data control system and data management apparatus for use therewith |
| 04/30/1991 | US5012138 Interface circuit for asychronous data transfer |
| 04/24/1991 | EP0424116A2 Buffer control apparatus |
| 04/23/1991 | US5010519 Dynamic semiconductor memory device formed by 2-transistor cells |
| 04/23/1991 | US5010508 Prenormalization for a floating-point adder |
| 04/23/1991 | US5010345 Data compression method |
| 04/23/1991 | US5010344 Method of decoding compressed data |
| 04/17/1991 | CN1012396B Message fifo buffer controller |
| 04/17/1991 | CN1012395B Message fifo buffer controller |
| 04/10/1991 | EP0421627A2 Memory device |
| 04/03/1991 | EP0420579A2 Josephson integrated circuit having an output interface capable of providing output data with reduced clock rate |
| 04/03/1991 | EP0420409A2 Interface circuit |
| 04/03/1991 | CN1050450A Apparatus and method for asynchronously delivering control elements with pipe interface |
| 04/03/1991 | CN1012294B Stand-by heat memory copy system |
| 03/27/1991 | EP0419066A2 Computer system having apparatus for asynchronously delivering control elements with a pipe interface |
| 03/27/1991 | EP0418447A1 Device for controlling the enqueuing and dequeuing operations of messages in a memory |
| 03/26/1991 | US5003558 Data synchronizing buffers for data processing channels |
| 03/26/1991 | US5003501 Precharge circuitry and bus for low power applications |
| 03/26/1991 | US5003308 Serial data receiver with phase shift detection |
| 03/26/1991 | US5003307 Data compression apparatus with shift register search means |
| 03/20/1991 | EP0417903A2 Memory with synchronous/asynchronous memory address buffer |
| 03/20/1991 | EP0417314A1 Serial data receiving circuit |
| 03/19/1991 | US5001663 Programmable digital circuit for performing a matrix multiplication |
| 03/19/1991 | US5001478 Method of encoding compressed data |
| 03/13/1991 | EP0416513A2 Fifo memory device |
| 03/13/1991 | EP0416281A2 Data buffer |
| 03/12/1991 | US4999796 Sticky bit detection and shifting logic |
| 03/07/1991 | DE4022396A1 Matching ADC output to computing system input - converts binary ADC output signal into two's complement form with doubled resolution |
| 03/06/1991 | WO1991003880A1 Improved data compression apparatus |
| 03/06/1991 | EP0415862A2 Optimized I/O buffers |
| 02/28/1991 | DE4026222A1 Data transfer circuit with processor clock phase matching - has time phase correction device accessed for reading and writing using different clocks |
| 02/19/1991 | US4995005 Memory device which can function as two separate memories or a single memory |
| 02/19/1991 | US4995003 Serial data transfer circuit for a semiconductor memory device |
| 02/13/1991 | EP0412267A2 Asynchronous high-speed data interface |
| 02/12/1991 | US4992973 Data transmission apparatus with loopback topology |
| 02/12/1991 | US4992931 Data alignment correction apparatus for properly formatting data structures for different computer architectures |
| 02/07/1991 | WO1990016025A3 Data store connection |
| 02/06/1991 | EP0411692A2 Last-in first-out memory and data repacker for use therein |
| 02/06/1991 | EP0411691A2 Memory architecture and circuit for hashing |
| 02/05/1991 | US4991130 Normalization control system for floating point arithmetic operation |
| 01/30/1991 | EP0410515A1 Rotation method for a word of "p" binary elements and device in which said method is used |
| 01/29/1991 | US4988998 Data compression system for successively applying at least two data compression methods to an input data stream |
| 01/23/1991 | EP0409449A2 Interleaved sensing system for fifo and burst-mode memories |
| 01/23/1991 | EP0397686A4 Apparatus for efficiently packing data in a buffer |
| 01/16/1991 | EP0408132A1 A system for processing data organized in files and a control module for use therein |
| 01/16/1991 | EP0407642A1 Buffer memory arrangement |
| 01/15/1991 | US4985867 Semiconductor memory circuit |
| 01/15/1991 | US4985848 High speed image processing system using separate data processor and address generator |
| 01/15/1991 | US4985701 Time-division bit number conversion circuit |
| 01/09/1991 | EP0407177A2 Bit sequence reversing device |
| 01/08/1991 | US4984189 Digital data processing circuit equipped with full bit string reverse control circuit and shifter to perform full or partial bit string reverse operation and data shift operation |
| 01/02/1991 | EP0405577A2 Frame conversion circuit |
| 01/02/1991 | EP0405459A2 Data write control circuit having word length conversion function |
| 01/01/1991 | US4982353 Subsampling time-domain digital filter using sparsely clocked output latch |
| 12/30/1990 | CA2020015A1 Frame conversion circuit |
| 12/27/1990 | WO1990016025A2 Data store connection |
| 12/27/1990 | EP0404535A2 Bandwidth compression device |
| 12/25/1990 | US4980852 Non-locking queueing mechanism for enabling a receiver device to read from a queue without access synchronization with a sending device |
| 12/25/1990 | US4980851 Reduced power pipelined static data transfer apparatus |
| 12/20/1990 | DE4019135A1 Serieller speicher auf ram-basis mit parallelem voraus-lesen Serial store on ram base with parallel read-ahead |
| 12/18/1990 | US4979141 Technique for providing a sign/magnitude subtraction operation in a floating point computation unit |
| 12/18/1990 | US4979097 Method and apparatus for interconnecting busses in a multibus computer system |
| 12/13/1990 | WO1990015385A1 System and method for cyclical, offset multiport register operation |
| 12/12/1990 | EP0401340A1 Method and apparatus for handling high speed data. |
| 12/11/1990 | US4977535 Method of computation of normalized numbers |
| 12/05/1990 | EP0400734A1 Programmable binary signal delay device and application to an error correcting code device |
| 11/27/1990 | US4974241 Counter employing exclusive NOR gate and latches in combination |
| 11/22/1990 | EP0397686A1 Apparatus for efficiently packing data in a buffer. |
| 11/15/1990 | WO1990013866A1 A programmable digital circuit for performing a matrix multiplication |
| 11/14/1990 | EP0397358A1 Parallel to serial converter |
| 11/14/1990 | EP0396669A1 Method and apparatus for detecting impending overflow and/or underrun of elasticity buffer. |
| 11/13/1990 | US4970591 Control of an encoding parameter according to a ratio of a moving picture area in each frame |