| Patents for G06F 5 - Methods or arrangements for data conversion without changing the order or content of the data handled (8,116) |
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| 03/08/1994 | US5293409 For temporary storage of digital information |
| 03/08/1994 | US5293164 Data compression with pipeline processor having separate memories |
| 03/02/1994 | EP0584992A2 Text compression technique using frequency ordered array of word number mappers |
| 03/02/1994 | EP0584862A1 Multiplexing arrangement |
| 03/01/1994 | US5291468 Method and apparatus for synchronizing the readout of a sequential media device with a separate clocked device |
| 02/24/1994 | DE4227776A1 Shift register for input handling in arithmetic circuits - has inputs located in shift registers with automatic decimal point shift control for addition and subtraction of coded numbers |
| 02/24/1994 | DE4225181C1 Frame structuring device for digital transmission system - uses temporary memories of equal depth on transmission and reception side with multiplexer-demultiplexer control |
| 02/22/1994 | US5289507 Clock dejitter circuits for regenerating jittered clock signals |
| 02/17/1994 | WO1994003983A1 Single clock cycle data compressor/decompressor with a string reversal mechanism |
| 02/17/1994 | DE4226952A1 Frame synchroniser for telemetry system - has pair of FIFO memory stages operating alternately and coupled to serial to parallel converter for high rates |
| 02/16/1994 | EP0582907A2 Data compression apparatus and method using matching string searching and Huffman encoding |
| 02/16/1994 | EP0582666A1 Method and apparatus for buffering data within stations of a communication network |
| 02/09/1994 | EP0582273A2 Decoding circuit for variable length code |
| 02/03/1994 | DE4322995A1 Decoding system for variable length codes based upon look=up table - provides access by reduced address generated by data-bank selector and bit selector circuits |
| 02/02/1994 | EP0581608A1 Programmable difference flag logic |
| 02/01/1994 | US5283899 Data processing system |
| 02/01/1994 | US5283787 Synchronization of digital audio signals |
| 02/01/1994 | US5283763 Memory control system and method |
| 01/26/1994 | EP0579595A1 Clock dejitter circuits for regenerating jittered clock signals |
| 01/25/1994 | US5282275 Address processor for a signal processor |
| 01/19/1994 | EP0579375A2 Difference flag circuit with offset counter |
| 01/18/1994 | US5280584 Two-way data transfer apparatus |
| 01/18/1994 | US5280575 Apparatus for cell format control in a spread sheet |
| 01/12/1994 | EP0577773A1 Vocabulary memory allocation for adaptive data compression of frame-multiplexed traffic |
| 01/11/1994 | US5278956 Data communications device |
| 01/05/1994 | EP0577216A1 Time delay control for serial digital video interface audio receiver buffer |
| 01/05/1994 | EP0576711A1 Data processing system with several clock frequencies |
| 01/04/1994 | US5276898 System for selectively compressing data frames based upon a current processor work load identifying whether the processor is too busy to perform the compression |
| 01/04/1994 | US5276891 Alignment of sign, data, edit byte operand results for storage in memory |
| 01/02/1994 | CA2099689A1 Time delay control for serial digital video interface audio receiver buffer |
| 12/29/1993 | EP0575829A2 Serial access memory with column address counter and pointers |
| 12/28/1993 | US5274647 Elastic buffer with error detection using a hamming distance circuit |
| 12/28/1993 | US5274600 First-in first-out memory |
| 12/28/1993 | US5274589 Method and apparatus for writing and reading data to/from a memory |
| 12/22/1993 | EP0574598A1 Data buffer |
| 12/21/1993 | US5272728 Preamble length adjustment method in communication network and independent synchronization type serial data communication device |
| 12/21/1993 | US5272675 High-speed first-in first-out memory flexible to increase the memory capacity |
| 12/21/1993 | US5272478 Method and apparatus for entropy coding |
| 12/21/1993 | CA2006704C Total sum calculation circuit capable of rapidly calculating a total sum of more than two input data represented by a floating point representation |
| 12/15/1993 | EP0574144A2 Parallelized difference flag logic |
| 12/14/1993 | US5270981 Field memory device functioning as a variable stage shift register with gated feedback from its output to its input |
| 12/09/1993 | WO1993025031A1 Method and equipment for monitoring the fill rate of an elastic buffer memory in a synchronous digital telecommunication system |
| 12/07/1993 | US5268856 Bit serial floating point parallel processing system and method |
| 12/01/1993 | EP0572367A1 A method and an arrangement for adapting the rate at which data information is read from a memory to the rate at which data information is written into the memory |
| 12/01/1993 | EP0572366A1 A method and an arrangement relating to memory write-in and read-out |
| 12/01/1993 | EP0571683A1 High performance data re-alignment mechanism with multiple buffers in a memory access control device |
| 11/30/1993 | US5267191 FIFO memory system |
| 11/24/1993 | EP0570877A1 Tributary ambiguity resolution for elastic store control |
| 11/23/1993 | US5265259 Blocks and bits sequence reversing device using barrel shift |
| 11/18/1993 | EP0570143A2 Method and apparatus for interfacing a serial data signal |
| 11/16/1993 | US5262997 Extendable FIFO |
| 11/16/1993 | US5262996 First-in first-out |
| 11/16/1993 | US5262971 Bidirectional shifter |
| 11/10/1993 | CN1022723C Two-way data transfer device |
| 11/09/1993 | US5261064 Burst access memory |
| 11/09/1993 | US5260940 Circuit arrangement for bit rate adaptation |
| 11/09/1993 | US5260887 Bit data shift amount detector |
| 11/09/1993 | US5260613 Real-data FFT buffer |
| 11/03/1993 | EP0568305A2 Data compression |
| 11/03/1993 | EP0478616B1 Method and apparatus for data store connection |
| 11/02/1993 | US5258855 Information processing methodology |
| 10/28/1993 | WO1993021595A1 Media composer including pointer-based display of sequentially stored samples |
| 10/28/1993 | WO1993021575A1 A high density buffer memory architecture and method |
| 10/27/1993 | CN1022591C Address processor for signal processor |
| 10/26/1993 | US5257261 Methods and apparatus for concatenating a plurality of lower level SONET signals into higher level sonet signals |
| 10/19/1993 | US5255242 Sequential memory |
| 10/19/1993 | US5255239 Bidirectional first-in-first-out memory device with transparent and user-testable capabilities |
| 10/19/1993 | US5255238 First-in first-out semiconductor memory device |
| 10/14/1993 | WO1993020516A1 Virtual fifo peripheral interface system and method |
| 10/14/1993 | WO1993020506A1 Semiconductor floor plan and method for a register renaming circuit |
| 10/12/1993 | US5253325 Data compression with dynamically compiled dictionary |
| 10/06/1993 | EP0564118A1 Serial data transfer apparatus and method |
| 10/05/1993 | US5251314 System for converting from one document type to a plurality of document types allowing accurate reversal therefrom using tables containing indications regarding non-transformable elements |
| 09/30/1993 | WO1993018922A1 Apparatus and method for processing information, and additional control device used therein |
| 09/28/1993 | US5249271 Buffer memory data flow controller |
| 09/28/1993 | US5249148 Method and apparatus for performing restricted modulo arithmetic |
| 09/21/1993 | US5247652 Parallel to serial converter enabling operation at a high bit rate with slow components by latching sets of pulses following sequential delays equal to clock period |
| 09/21/1993 | US5247471 Radix aligner for floating point addition and subtraction |
| 09/21/1993 | CA1322419C Method and apparatus for detecting impending overflow and/or underrun of elasticity buffer |
| 09/16/1993 | WO1993018595A1 Methods and apparatus for retiming and realignment of sts-1 signals into sts-3 type signal |
| 09/16/1993 | DE4304702A1 High speed serial to parallel converter for data transmission - has input data stream fed to pair of parallel multi stage registers with outputs generated via selector controlled by compressor |
| 09/15/1993 | EP0560020A2 Digital signal processing function appearing as hardware FIFO |
| 09/15/1993 | EP0559824A1 Binary data communication system |
| 09/15/1993 | EP0559649A1 Method and means for transferring a data payload from a first sonet signal to a sonet signal of different frequency |
| 09/14/1993 | US5245614 Vocabulary memory allocation for adaptive data compression of frame-multiplexed traffic |
| 09/14/1993 | US5245337 Data compression with pipeline processors having separate memories |
| 09/02/1993 | WO1993017381A1 System for dynamic segmentation using mixed data model |
| 08/31/1993 | US5241644 Queue having long word length |
| 08/31/1993 | US5241490 Fully decoded multistage leading zero detector and normalization apparatus |
| 08/25/1993 | CN1075563A Improved method for interchange code conversion of multi-byte character string characters |
| 08/24/1993 | US5239387 Buffering control for accommodating variable data exchange rates |
| 08/24/1993 | CA1321650C Floating point unit computation techniques |
| 08/18/1993 | EP0555382A1 Address generator for circular buffer. |
| 08/17/1993 | US5237701 Data unpacker using a pack ratio control signal for unpacked parallel fixed m-bit width into parallel variable n-bit width word |
| 08/17/1993 | US5237661 Buffer management method and system therefor using an I/O buffer on main memory and utilizing virtual memory and page fixing |
| 08/17/1993 | US5237660 Control method and apparatus for controlling the data flow rate in a FIFO memory, for synchronous SCSI data transfers |
| 08/11/1993 | EP0511971A4 Unbiased bit disposal apparatus and method |
| 08/05/1993 | WO1993012481A3 Buffer and frame indexing |
| 08/03/1993 | US5233693 First-in first-out storage facility having bypassing loop thereof |
| 07/28/1993 | CN1074768A Method for buffering bandwidth data from an input device |