| Patents for G06F 5 - Methods or arrangements for data conversion without changing the order or content of the data handled (8,116) |
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| 10/28/1992 | EP0321568B1 Pipeline control system |
| 10/21/1992 | EP0509722A2 Data transfer system |
| 10/21/1992 | EP0365526B1 Asynchronous time division communication system |
| 10/20/1992 | US5157696 Digital signal time difference correcting circuit |
| 10/20/1992 | US5157655 Apparatus for generating a ds-3 signal from the data component of an sts-1 payload signal |
| 10/20/1992 | US5157633 Fifo memory device |
| 10/14/1992 | EP0508811A2 Double buffer type elastic store comprising a pair of data memory blocks |
| 10/14/1992 | EP0424407A4 Intermediate spreadsheet structure |
| 10/14/1992 | CN1065367A Clock rate matching in independent networks |
| 10/13/1992 | US5155830 Data processing system capable of performing a direct memory access transfer of data stored in a physical area in a memory |
| 10/13/1992 | US5155698 Barrel shifter circuit having rotation function |
| 10/07/1992 | EP0507571A2 Receiving buffer control system |
| 10/07/1992 | EP0507439A2 Buffering control for accommodating variable data exchange rates |
| 10/06/1992 | US5153846 Digital shift register using random access memory |
| 10/06/1992 | US5153591 Method and apparatus for encoding, decoding and transmitting data in compressed form |
| 10/06/1992 | CA1308449C Device for producing a delay of one high rate binary data stream at least |
| 10/01/1992 | WO1992017023A1 Information processing methodology |
| 09/30/1992 | EP0505764A2 Modular interface |
| 09/29/1992 | US5151995 Method and apparatus for producing successive calculated results in a high-speed computer functional unit using low-speed VLSI components |
| 09/22/1992 | US5150389 Shift register |
| 09/22/1992 | US5150386 Clock multiplier/jitter attenuator |
| 09/22/1992 | US5150313 Parallel pulse processing and data acquisition for high speed, low error flow cytometry |
| 09/22/1992 | US5150066 Programmable digital signal delay device and its use for a error correction code device |
| 09/15/1992 | US5148161 Digital signal processor for fixed and floating point data |
| 09/12/1992 | CA2059001A1 Scsi controller |
| 09/09/1992 | EP0502544A2 A data shifting circuit of a central processing unit |
| 09/08/1992 | US5146592 High speed image processing computer with overlapping windows-div |
| 09/08/1992 | US5146577 Serial data circuit with randomly-accessed registers of different bit length |
| 09/03/1992 | WO1992015055A1 Circuit for connecting a microprocessor system with a communications channel |
| 09/01/1992 | US5144581 Apparatus including atomic probes utilizing tunnel current to read, write and erase data |
| 09/01/1992 | US5144573 Barrel shifter with parity bit generator |
| 09/01/1992 | US5144570 Normalization estimator |
| 08/25/1992 | US5142529 Method and means for transferring a data payload from a first SONET signal to a SONET signal of different frequency |
| 08/25/1992 | US5142494 Memory based line-delay architecture |
| 08/25/1992 | US5142282 Data compression dictionary access minimization |
| 08/23/1992 | WO1992015159A1 Clock rate matching in independent networks |
| 08/20/1992 | DE4104957A1 Schaltung zur verbindung eines mikroprozessorsystems mit einem kommunikationskanal Circuit for connection of a microprocessor system having a communication channel |
| 08/12/1992 | EP0498201A2 Generic high bandwidth adapter architecture |
| 08/12/1992 | CN1017836B Microcomputer multichannel and multiple electric parameters transducer |
| 08/11/1992 | US5138637 First-in-first-out buffer |
| 08/11/1992 | US5138315 Arrangements for variable-length encoding and decoding of digital signals |
| 08/04/1992 | US5136718 Communications arrangement for digital data processing system employing heterogeneous multiple processing nodes |
| 08/04/1992 | US5136292 Serial data receiving circuit for serial to parallel conversion |
| 08/04/1992 | US5136291 Transmitting binary data files using electronic mail |
| 07/28/1992 | US5134562 Fifo register device adaptively changing a stage number in dependency on a bus cycle |
| 07/22/1992 | EP0495217A2 Sequential memory |
| 07/21/1992 | US5133078 Serial frame processing system in which validation and transfer of a frame's data from input buffer to output buffer proceed concurrently |
| 07/21/1992 | US5133062 RAM buffer controller for providing simulated first-in-first-out (FIFO) buffers in a random access memory |
| 07/21/1992 | US5132898 System for processing data having different formats |
| 07/21/1992 | CA1305560C Method and apparatus for interconnecting busses in a multibus computer system |
| 07/14/1992 | US5130941 Dynamic barrel shifter |
| 07/14/1992 | US5130940 Barrel shifter for data shifting |
| 07/08/1992 | EP0493834A2 Address generating circuit |
| 07/07/1992 | US5129060 High speed image processing computer |
| 07/01/1992 | EP0493138A2 Memory circuit |
| 07/01/1992 | EP0492025A1 High-speed multi-port FIFO buffer circuit |
| 06/30/1992 | US5126963 Hardware arrangement for floating-point multiplication and operating method therefor |
| 06/30/1992 | US5126598 Josephson integrated circuit having an output interface capable of providing output data with reduced clock rate |
| 06/24/1992 | EP0491370A2 Sequential memory |
| 06/17/1992 | DE4039765A1 Data signal stop bit removing circuit - uses phase regulating loop with phase comparator matching frequency of write and read clock with read clock phase adjustment |
| 06/16/1992 | US5123099 Hot standby memory copy system |
| 06/16/1992 | US5122988 Data stream smoothing using a FIFO memory |
| 06/11/1992 | WO1992010035A1 Binary data communication system |
| 06/10/1992 | EP0489504A2 Bidirectional FIFO buffer for interfacing between two buses |
| 06/10/1992 | EP0489248A2 Address control for a first-in first-out memory |
| 06/09/1992 | US5121480 Data recording system buffer management and multiple host interface control |
| 06/09/1992 | US5121346 Difference comparison between two asynchronous pointers and a programmable value |
| 05/29/1992 | WO1992009032A1 Unbiased bit disposal apparatus and method |
| 05/26/1992 | US5117395 Expansible FIFO memory for accommodating added memory stages in a multistage memory with common control signals |
| 05/26/1992 | US5117382 Semiconductor integrated circuit for performing an arithmetic operation including bipolar and mos transistors |
| 05/21/1992 | DE4029977A1 Digital multiplying and dividing circuitry - has expanded logic function for handling decimal point processing |
| 05/20/1992 | EP0486143A2 Parallel processing of data |
| 05/20/1992 | EP0485776A2 A method for executing graphics pixel packing instructions in a data processor |
| 05/19/1992 | US5115496 Queue device capable of quickly transferring a digital signal unit of a word length different from a single word length |
| 05/14/1992 | WO1992008192A1 System and method for dynamically linking code segments in real time |
| 05/14/1992 | WO1992008186A1 Address generator for circular buffer |
| 05/13/1992 | EP0485081A2 Data compression dictionary access minimization logic |
| 05/13/1992 | EP0485021A1 Elastic buffer |
| 05/13/1992 | EP0484652A2 First-in-first-out buffer |
| 05/12/1992 | US5113368 Circuit for delaying at least one high bit rate binary data train |
| 05/06/1992 | EP0483970A1 Dynamically linking code segments in a multiprocessor system |
| 05/06/1992 | EP0483967A2 Apparatus for increasing the number of registers available in a computer processor |
| 05/06/1992 | EP0483441A1 System arrangement for storing data on a FIFO basis |
| 05/06/1992 | CN1060916A Method and apparatus for maintaining cache integrity whenever cpu. write to rom. operation is performed with rom. mapped to ram. |
| 05/05/1992 | US5111488 Doubling/dividing device for a series bit flow |
| 05/05/1992 | US5111385 Parallel-mode data transfer apparatus using sector memories |
| 05/01/1992 | WO1992008304A1 Apparatus for generating a ds-3 signal from the data component of an sts-1 payload signal |
| 04/29/1992 | EP0482752A2 Methods and apparatus for maintaining cache integrity |
| 04/28/1992 | US5109488 Data processing system buffering sequential data for cyclically recurrent delay times, memory address generator for use in such system |
| 04/28/1992 | US5109348 High speed image processing computer |
| 04/28/1992 | CA1299759C Control interface for transferring data between a data processing unit andinput/output devices |
| 04/22/1992 | EP0481751A2 Pipeline circuitry for allowing the comparison of the relative difference between two asynchronous pointers and a programmable value |
| 04/21/1992 | US5107465 Asynchronous/synchronous pipeline dual mode memory access circuit and method |
| 04/21/1992 | US5107462 Self timed register file having bit storage cells with emitter-coupled output selectors for common bits sharing a common pull-up resistor and a common current sink |
| 04/15/1992 | EP0480115A1 Improved data compression/coding method and device for implementing said method |
| 04/15/1992 | CN1060377A Two-way data transfer device |
| 04/09/1992 | DE4031897A1 Electronic null input circuit for four-field encoding - ensures correct positioning of decimal point when results include only numerals above zero |
| 04/09/1992 | DE4031603A1 Electronic result shift circuit positioning numbers correctly - processes only numbers 1 to 9 and decimal points but not nulls to display field |
| 04/08/1992 | EP0478616A1 Method and apparatus for data store connection. |
| 04/07/1992 | US5103467 Asynchronous voice reconstruction for a digital communication system |