Patents
Sitemap › H03 - Basic electronic circuitry › H03K - Pulse technique › H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996)
10/2001
10/23/2001US6307401 Low voltage differential dual receiver
10/23/2001US6307399 High speed buffer circuit with improved noise immunity
10/23/2001US6307397 Reduced voltage input/reduced voltage output repeaters for high capacitance signal lines and methods therefor
10/23/2001US6307396 Low-consumption TTL-CMOS input buffer stage
10/23/2001US6307234 Complementary MOS semiconductor device
10/23/2001CA2225803C Arrangement and method relating to digital information
10/18/2001WO2001078148A1 Electrostatic discharge (esd) protection circuit
10/18/2001WO2001077700A1 A method and apparatus for testing digital circuitry
10/18/2001WO2000044095A9 Fpga integrated circuit having embedded sram memory blocks and interconnect channel for broadcasting address and control signals
10/18/2001US20010030566 Load equalization in digital delay interpolators
10/18/2001US20010030561 Signal output device and method for sending signals at multiple transfer rates while minimizing crosstalk effects
10/18/2001US20010030557 Electrical load driving device
10/18/2001US20010030555 Configurable lookup table for programmable logic devices
10/18/2001US20010030554 Programmable logic arrays
10/18/2001US20010030239 Circuit configuration and method for authenticating the content of a memory area
10/18/2001DE10118144A1 Ansteuervorrichtung für eine elektrische Last Control device for an electrical load
10/17/2001EP1146432A2 Reconfiguration method for programmable components during runtime
10/17/2001EP1146412A2 High speed serial link for fully duplexed data communication
10/17/2001EP1145435A1 Single ended domino compatible dual function generator circuits
10/17/2001EP1145426A1 Data pulse receiver
10/17/2001EP1110319A4 Dc output level compensation circuit
10/17/2001EP0694231B1 Noise isolated i/o buffer
10/17/2001EP0591342B1 Basic cell architecture for mask programmable gate array
10/17/2001CN1317879A Three-state comparator, bidirectional combination of three-state comparators and multi-threshold drive mode
10/17/2001CN1317878A Width-regualting combination of three-state comparator circuit and analog drive mode of logic circuit
10/17/2001CN1317877A Unidirectional combination of three-state comparators and analog drive mode of logic circuit
10/16/2001US6304941 Method and apparatus for reducing processor operations when adding a new drive to a raid-6 drive group
10/16/2001US6304495 Logic interface circuit and semiconductor memory device using this circuit
10/16/2001US6304123 Data storage circuits using a low threshold voltage output enable circuit
10/16/2001US6304120 Buffer circuit operating with a small through current and potential detecting circuit using the same
10/16/2001US6304112 Integrated circuit provided with a fail-safe mode
10/16/2001US6304110 Buffer using dynamic threshold-voltage MOS transistor
10/16/2001US6304105 Level shifter circuit
10/16/2001US6304104 Method and apparatus for reducing worst case power
10/16/2001US6304103 FPGA using RAM control signal lines as routing or logic resources after configuration
10/16/2001US6304102 Repairable dynamic programmable logic array
10/16/2001US6304101 Programmable logic device, information processing system, method of reconfiguring programmable logic device and method compressing circuit information for programmable logic device
10/16/2001US6304099 Method and structure for dynamic in-system programming
10/16/2001US6304069 Low power consumption multiple power supply semiconductor device and signal level converting method thereof
10/11/2001WO2001076075A1 Error correcting integrated circuit and method
10/11/2001WO2001076071A2 High voltage cmos signal driver system and method
10/11/2001WO2001076070A1 Methods and apparatus for full i/o functionality and blocking of backdrive current
10/11/2001WO2000076068A3 Single rail domino logic for four-phase clocking scheme
10/11/2001US20010028585 Integrated circuit with a differential amplifier
10/11/2001US20010028278 Temperature dependent circuit, and current generating circuit, inverter and oscillation circuit using the same
10/11/2001US20010028271 Line driver
10/11/2001US20010028263 Power on reset circuit
10/11/2001US20010028261 Driver circuit
10/11/2001US20010028258 Circuit for inhibiting power consumption in low voltage dynamic logic
10/11/2001US20010028257 Block symmetrization in a field programmable gate array
10/10/2001EP1143452A2 Memory circuitry for programmable logic integrated circuit devices
10/10/2001EP1143336A1 FPGA with increased cell utilization
10/10/2001EP1142119A1 On-chip decoupling capacitor system with parallel fuse
10/10/2001EP1142115A1 A method and apparatus for reducing signal transmission delay using skewed gates
10/10/2001EP1142020A1 Cmos high-to-low voltage buffer
10/10/2001EP1141962A2 Seu hardening circuit
10/10/2001EP1141841A1 Hot-swappable high speed point-to-point interface
10/10/2001EP1048109A4 Current control technique
10/10/2001CN1316827A Level offset passing gate circuit
10/09/2001US6301643 Multi-environment data consistency
10/09/2001US6301305 Transmitting apparatus for outputting a binary signal
10/09/2001US6300821 Output buffer circuit having changeable output impedance
10/09/2001US6300819 Circuit including forward body bias from supply voltage and ground nodes
10/09/2001US6300815 Voltage reference overshoot protection circuit
10/09/2001US6300805 Circuit for auto-zeroing a high impedance CMOS current driver
10/09/2001US6300802 Output buffer with programmable voltage swing
10/09/2001US6300801 Or gate circuit and state machine using the same
10/09/2001US6300800 Integrated circuit I/O buffer with series P-channel and floating well
10/09/2001US6300799 Signal line driver having reduced transmission delay time and reduced power consumption
10/09/2001US6300798 Method and apparatus for controlling compensated buffers
10/09/2001US6300794 Programmable logic device with hierarchical interconnection resources
10/09/2001US6300793 Scalable multiple level tab oriented interconnect architecture
10/09/2001US6300792 Programmable input/output pin signal multiplexing/demultiplexing circuitry for integrated circuits
10/04/2001WO2001074124A1 Simultaneous switching noise minimization technique for power lines using dual layer power line mutual inductors
10/04/2001WO2001073949A1 Electrical id circuit and method
10/04/2001US20010027504 Noise reduction system and method for reducing switching noise in an interface to a large width bus
10/04/2001US20010026495 Semiconductor integrated circuit device and method of activating the same
10/04/2001US20010026485 Decoder element for producing an output signal having three different potentials
10/04/2001US20010026187 Booster, IC card having the same, and electronic equipment having the same
10/04/2001US20010026185 Device and method for limiting the extent to which circuits in integrated circuit dice electrically load bond pads and other circuit nodes in the dice
10/04/2001US20010026182 Circuit configuration
10/04/2001US20010026181 Current comparison type latch
10/04/2001US20010026178 Output buffer circuit and control method therefor
10/04/2001US20010026171 Semiconductor integrated circuit
10/04/2001US20010026170 Electronic circuit provided with a digital driver for driving a capacitive load
10/04/2001US20010026169 Semiconductor integrated circuit having transistors for cutting-off subthreshold current
10/04/2001US20010025967 Semiconductor device
10/04/2001US20010025913 Drive apparatus for CCD image sensor
10/04/2001EP1139567A1 Level converter circuit
10/04/2001EP1051803A4 Slew rate control circuit
10/03/2001CN1316132A Circuit arrangement and optical read/write device including the circuit arrangement
10/03/2001CN1315784A High-speed digital signal driver
10/02/2001US6297686 Semiconductor integrated circuit for low-voltage high-speed operation
10/02/2001US6297685 High-speed fully-compensated low-voltage differential driver/translator circuit arrangement
10/02/2001US6297679 Input buffer
10/02/2001US6297678 Circuit for rapidly charging a system net
10/02/2001US6297677 Method for a dynamic termination logic driver with improved slew rate control
10/02/2001US6297675 Semiconductor integrated circuit and semiconductor integrated circuit system having serially interconnectable data buses
10/02/2001US6297674 Semiconductor integrated circuit for low power and high speed operation
10/02/2001US6297672 CMOS integrated circuit
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