| Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996) |
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| 10/02/2001 | US6297669 Low-technology inexpensive logic module system |
| 10/02/2001 | US6297668 Serial device compaction for improving integrated circuit layouts |
| 10/02/2001 | US6297667 Circuits and sequences for enabling remote access to and control of non-adjacent cells in a locally self-reconfigurable processing system composed of self-dual processing cells |
| 10/02/2001 | US6297666 Fully programmable and configurable application specific integrated circuit |
| 10/02/2001 | US6297665 FPGA architecture with dual-port deep look-up table RAMS |
| 10/02/2001 | CA2258358C Low power multiplier for cpu and dsp |
| 09/27/2001 | WO2001071915A2 Load capacitance compensated buffer, apparatus and method thereof |
| 09/27/2001 | US20010025012 Superconductor signal amplifier |
| 09/27/2001 | US20010024381 Current sense amplifier circuit |
| 09/27/2001 | US20010024137 Driver circuit |
| 09/27/2001 | US20010024136 Semiconductor integrated circuit compensating variations of delay time |
| 09/27/2001 | US20010024133 Output driver circuit |
| 09/27/2001 | US20010024130 Level converter circuit |
| 09/26/2001 | EP1137185A1 Hybrid circuit having a current source controlled by a comparator |
| 09/26/2001 | EP1137184A1 Voltage level shifting circuit |
| 09/26/2001 | EP1135859A1 Method and apparatus for logic synchronization |
| 09/26/2001 | CN1315079A Driving circuit |
| 09/25/2001 | US6295572 Integrated SCSI and ethernet controller on a PCI local bus |
| 09/25/2001 | US6295230 Nonvolatile configuration cells and cell arrays |
| 09/25/2001 | US6294954 Adaptive dead time control for switching circuits |
| 09/25/2001 | US6294947 Asymmetrical current steering output driver with compact dimensions |
| 09/25/2001 | US6294943 Method of designing fail-safe CMOS I/O buffers whose external nodes accept voltages higher than the maximum gate oxide operating voltage |
| 09/25/2001 | US6294934 Current control technique |
| 09/25/2001 | US6294933 Method and apparatus for low power differential signaling to reduce power |
| 09/25/2001 | US6294932 Input circuit, output circuit, input-output circuit and method of processing input signals |
| 09/25/2001 | US6294931 Systems and methods for maintaining board signal integrity |
| 09/25/2001 | US6294930 FPGA with a plurality of input reference voltage levels |
| 09/25/2001 | US6294929 Balanced-delay programmable logic array and method for balancing programmable logic array delays |
| 09/25/2001 | US6294928 Programmable logic device with highly routable interconnect |
| 09/25/2001 | US6294927 Configurable cell for customizable logic array device |
| 09/25/2001 | US6294926 Very fine-grain field programmable gate array architecture and circuitry |
| 09/25/2001 | US6294925 Programmable logic device |
| 09/25/2001 | US6294924 Dynamic termination logic driver with improved slew rate control |
| 09/20/2001 | WO2001069837A2 Clock data recovery circuitry associated with programmable logic device circuitry |
| 09/20/2001 | WO2001069785A1 Electronic circuit provided with a digital driver for driving a capacitive load |
| 09/20/2001 | US20010023491 Device for testing digital signal processor in digital video disc reproducing apparatus |
| 09/20/2001 | US20010023489 Microprocessor having low power internal oscillator capabilities |
| 09/20/2001 | US20010022715 Power semiconductor circuit |
| 09/20/2001 | US20010022521 Semiconductor integrated circuit |
| 09/20/2001 | US20010022520 Level conversion circuit as well as semiconductor device and display unit comprising the same |
| 09/20/2001 | US20010022519 Programmable logic array integrated circuit architectures |
| 09/20/2001 | DE10062728A1 Level converter circuit includes input connection, signal input unit and number of signal converter units for outputting level-converted operating signals |
| 09/20/2001 | DE10011211A1 Secure switching device for on-off switching of electrical load has at least 2 switching elements each providing switch output for controlling load |
| 09/19/2001 | EP1134896A2 Programmable logic array integrated circuits |
| 09/19/2001 | EP1134894A2 Improvements in or relating to digital-to-analog converters |
| 09/19/2001 | EP1134893A2 Level shifter |
| 09/19/2001 | EP1133702A1 A reconfigurable integrated circuit with integrated debugging facilities for use in an emulation system |
| 09/19/2001 | CN1314027A Output driving circuit |
| 09/19/2001 | CN1313544A Simplification of interface of transmitting/receiving device |
| 09/19/2001 | CN1313214A Remote-controlled wireless antitheft device with self-check function for cars |
| 09/18/2001 | US6292930 Methods for configuring FPGA's having variable grain blocks and shared logic for providing time-shared access to interconnect resources |
| 09/18/2001 | US6292402 Prefetch write driver for a random access memory |
| 09/18/2001 | US6292116 Techniques and circuitry for accurately sampling high frequency data signals input to an integrated circuit |
| 09/18/2001 | US6292041 Circuit and method for limiting subthreshold leakage |
| 09/18/2001 | US6292037 Output circuit of semiconductor integrated circuit |
| 09/18/2001 | US6292031 Level shift circuit with common mode level control |
| 09/18/2001 | US6292029 Method and apparatus for reducing soft errors in dynamic circuits |
| 09/18/2001 | US6292028 Output circuit for a transmission system |
| 09/18/2001 | US6292027 Fast low-power logic gates and method for evaluating logic signals |
| 09/18/2001 | US6292026 Semiconductor device and electronic apparatus using the same |
| 09/18/2001 | US6292025 Integrated circuit device including CMOS tri-state drivers suitable for powerdown |
| 09/18/2001 | US6292022 Interconnect structure for a programmable logic device |
| 09/18/2001 | US6292021 FPGA structure having main, column and sector reset lines |
| 09/18/2001 | US6292020 Low-skew programmable control routing for a programmable logic device |
| 09/18/2001 | US6292019 Programmable logic device having configurable logic blocks with user-accessible input multiplexers |
| 09/18/2001 | US6292018 Configurable cellular array |
| 09/18/2001 | US6292017 Programmable logic device incorporating function blocks operable as wide-shallow RAM |
| 09/18/2001 | US6292016 Programmable logic with on-chip DLL or PLL to distribute clock |
| 09/18/2001 | US6292015 Semiconductor integrated circuit device including logic gate that attains reduction of power consumption and high-speed operation |
| 09/18/2001 | US6292014 Output buffer circuit for transmitting digital signals over a transmission line with preemphase |
| 09/18/2001 | US6291869 Semiconductor circuit device having hierarchical power supply structure |
| 09/18/2001 | US6291857 Semiconductor device of SOI structure with floating body region |
| 09/14/2001 | CA2340516A1 Driver circuit |
| 09/13/2001 | WO2001067705A2 A data transfer and management system |
| 09/13/2001 | WO2001067610A1 Security switching device and a system of security switching devices |
| 09/13/2001 | WO2001067609A2 High speed logic family |
| 09/13/2001 | WO2001067608A2 Domino logic family |
| 09/13/2001 | WO2001067607A2 Dynamic phase logic gate |
| 09/13/2001 | US20010021139 Semiconductor register element |
| 09/13/2001 | US20010020861 Delay circuit |
| 09/13/2001 | US20010020858 Latch circuit and semiconductor integrated circuit having the latch circuit with control signal having a large voltage amplitude |
| 09/13/2001 | US20010020853 High speed source synchronous signaling for interfacing VLSI CMOS circuits to transmission lines |
| 09/13/2001 | US20010020851 High-speed programmable interconnect |
| 09/13/2001 | CA2402307A1 A data transfer and management system |
| 09/13/2001 | CA2402196A1 High speed logic family |
| 09/13/2001 | CA2402194A1 Domino logic family |
| 09/12/2001 | EP1132827A2 Transceiver interface reduction in an USB device |
| 09/12/2001 | EP1097386A4 Adaptive driver with capacitive load sensing and method of operation |
| 09/12/2001 | CN1312609A Booster, integrated circuit cand with said booster and electronic apparatus |
| 09/11/2001 | US6289497 Method and apparatus for N-NARY hardware description language |
| 09/11/2001 | US6289496 Placement of input-output design objects into a programmable gate array supporting multiple voltage standards |
| 09/11/2001 | US6289494 Optimized emulation and prototyping architecture |
| 09/11/2001 | US6289447 Topology dependent compensation to improve performance of self-compensated components including processors based on physical relationship with other system components |
| 09/11/2001 | US6288599 High voltage input buffer made by a low voltage process and having a self-adjusting trigger point |
| 09/11/2001 | US6288593 Digital electronic circuit for use in implementing digital logic functions |
| 09/11/2001 | US6288590 High voltage protection input buffer |
| 09/11/2001 | US6288589 Method and apparatus for generating clock signals |
| 09/11/2001 | US6288586 Circuit for standby current reduction |
| 09/11/2001 | US6288582 Output circuit for semiconductor integrated circuit |
| 09/11/2001 | US6288580 Level-shifting circuit and input and output circuits using the same |