Patents
Sitemap › H03 - Basic electronic circuitry › H03K - Pulse technique › H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996)
11/2001
11/29/2001US20010047506 System and method for controlling current in an integrated circuit
11/29/2001US20010047446 Quantized queue length arbiter
11/29/2001US20010047249 Method for executing individual algorithms using a reconfigurable circuit, and apparatus for carrying out the method
11/29/2001US20010047220 Electric load driving device and method of using the same
11/29/2001US20010046158 Semiconductor memory device and method of fabricating the same
11/29/2001US20010045873 Noise reduction circuit and semiconductor device including the same
11/29/2001US20010045859 Signal potential conversion circuit
11/29/2001US20010045856 Delay circuit having low operating environment dependency
11/29/2001US20010045845 Interface circuit and signal transmission method
11/29/2001US20010045844 Configurable logic element with expander structures
11/29/2001US20010045579 Semiconductor device with reduced current consumption in standby state
11/29/2001DE10110157A1 Halbleitervorrichtung mit verringertem Stromverbrauch im Standby-Zustand Semiconductor device with reduced power consumption in standby mode
11/29/2001CA2409214A1 Block ram having multiple configurable write modes for use in a field programmable gate array
11/28/2001EP1158403A1 FPGA with configurable clock lines
11/28/2001EP1158402A1 FPGA with column set/reset lines
11/28/2001EP1157467A1 Electronic component with reduced inductive coupling
11/28/2001EP1157389A1 Double input buffer for track-and-hold amplifier
11/28/2001EP0746929B1 High speed differential receiver for data communications
11/28/2001CN1324460A Performance optimization through topology dependent compensation
11/28/2001CN1324087A New-type digital quantity output circuit
11/27/2001US6324679 Register transfer level power optimization with emphasis on glitch analysis and reduction
11/27/2001US6324239 Method and apparatus for a 1 of 4 shifter
11/27/2001US6323756 Data transmitter
11/27/2001US6323707 Output signal level control circuit in a semiconductor device
11/27/2001US6323704 Multiple voltage compatible I/O buffer
11/27/2001US6323703 Indirect output current sensing
11/27/2001US6323702 Integrated circuit devices having circuits therein for driving large signal line loads
11/27/2001US6323701 Scheme for reducing leakage current in an input buffer
11/27/2001US6323700 Double input buffer for track-and-hold amplifier
11/27/2001US6323698 Apparatus, method and system for providing LVS enables together with LVS data
11/27/2001US6323691 Logic circuit
11/27/2001US6323690 Logic circuit and its forming method
11/27/2001US6323688 Efficient half-cycle clocking scheme for self-reset circuit
11/27/2001US6323687 Output drivers for integrated-circuit chips with VCCQ supply compensation
11/27/2001US6323685 Threshold voltage scalable buffer with reference level
11/27/2001US6323684 Voltage tolerant interface circuit
11/27/2001US6323683 Low distortion logic level translator
11/27/2001US6323682 FPGA architecture with wide function multiplexers
11/27/2001US6323681 Circuits and methods for operating a multiplexer array
11/27/2001US6323680 Programmable logic device configured to accommodate multiplication
11/27/2001US6323678 Integrated circuit device with programmable junctions and method of designing such integrated circuit device
11/27/2001US6323677 Programmable logic device circuitry for improving multiplier speed and/or efficiency
11/27/2001US6323674 Technique and apparatus for terminating a transmission line
11/27/2001US6322653 Method for joining spiral wound pipes
11/22/2001WO2001089091A2 Method and apparatus for incorporating a multiplier into an fpga
11/22/2001US20010044924 Logic circuit module, method for designing a semiconductor integrated circuit using the same, and semiconductor integrated circuit
11/22/2001US20010044865 Transceiver interface reduction
11/22/2001US20010043105 Clock buffer circuit having short propagation delay
11/22/2001US20010043095 Output circuit
11/22/2001US20010043094 Output buffer for high and low voltage bus
11/22/2001US20010043092 Buffer circuit
11/22/2001US20010043085 Semiconductor integrated circuit
11/22/2001US20010043084 Semiconductor integrated circuit apparatus
11/22/2001US20010043083 Programmable logic array integrated circuits with blocks of logic regions grouped into super-blocks
11/22/2001US20010043082 Logic/memory circuit having a plurality of operating modes
11/22/2001US20010043081 Universal logic chip
11/22/2001DE10120086A1 Pufferschaltung mit geringem Rauschen Buffer circuit with low noise
11/22/2001DE10111999A1 Treiberschaltung Driver circuit
11/21/2001CN1323414A Method for executing individual algorithms by means of a reconfigurable circuit and device for carrying out such a method
11/21/2001CN1322975A Mountable electronic controller
11/21/2001CN1322953A Square matrix-shaped netted nanometer structure of composite oligomer DNA and inorganic nanometer crystal material
11/20/2001US6321282 Apparatus and method for topography dependent signaling
11/20/2001US6320454 Low power voltage regulator circuit for use in an integrated circuit device
11/20/2001US6320447 Circuit configuration with single-electron components, and operating method
11/20/2001US6320446 System for improving low voltage CMOS performance
11/20/2001US6320434 Circuit and method for generating a synchronous clock signal
11/20/2001US6320432 Output buffer circuit
11/20/2001US6320423 MOS logic circuit and semiconductor apparatus including the same
11/20/2001US6320422 Complementary source coupled logic
11/20/2001US6320420 Domino logic element realizing high speed dynamic logic circuit
11/20/2001US6320415 CMOS input/output control circuit capable of tolerating different voltage input
11/20/2001US6320413 Level conversion circuit
11/20/2001US6320412 Architecture and interconnect for programmable logic circuits
11/20/2001US6320411 Programmable logic array devices with enhanced interconnectivity between adjacent logic regions
11/20/2001US6320410 Heterogeneous CPLD logic blocks
11/20/2001US6320409 CMOS majority circuit
11/20/2001US6320408 Dual-sided undershoot-isolating bus switch
11/20/2001US6320407 Semiconductor circuit having output circuit whose slew rate can be adjusted, apparatus and method for automatically adjusting slew rate of output circuit in semiconductor circuit
11/20/2001US6320406 Methods and apparatus for a terminated fail-safe circuit
11/20/2001US6318911 Gated clock design supporting method, gated clock design supporting apparatus, and computer readable memory storing gated clock design supporting program
11/20/2001CA2245757C High speed, low voltage swing receiver for mixed supply voltage interfaces
11/20/2001CA2124745C High-speed cmos pseudo-ecl output driver
11/15/2001WO2001086813A2 Fpga lookup table with dual ended writes for ram and shift register modes
11/15/2001WO2001086812A2 Fpga lookup table with high speed read decoder
11/15/2001WO2001086513A2 Emulation circuit with a hold time algorithm, logic analyzer and shadow memory
11/15/2001US20010040834 Semiconductor integrated circuit device having a hierarchical power source configuration
11/15/2001US20010040471 I/O interface circuit, semiconductor chip and semiconductor system
11/15/2001US20010040469 Logic circuit with single charge pulling out transistor and semiconductor integrated circuit using the same
11/15/2001US20010040467 Method and apparatus for reducing soft errors in dynamic circuits
11/15/2001US20010040466 High speed low voltage differential signal driver having reduced pulse width distortion
11/15/2001US20010040465 Semiconductor device
11/14/2001EP1154438A2 Programmable circuit with preview function
11/14/2001EP1154435A2 Write circuitry for a synchronous ram
11/14/2001EP0961290B1 Flash memory with improved erasability and its circuitry
11/14/2001EP0667059B1 Logic structure and circuit for fast carry
11/14/2001CN1322314A Broken stack priority encoder
11/14/2001CN1322013A Integrated complementary metal oxide semiconductor circuit
11/13/2001US6317378 Buffer circuit
11/13/2001US6317367 FPGA with on-chip multiport memory
11/13/2001US6317001 Compensation of timing errors caused by dynamic thermal mismatch
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