Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
10/2013
10/10/2013WO2013150571A1 Semiconductor device
10/10/2013WO2013150194A1 Determination of the concentration of interstitial oxygen in a semiconductor sample
10/10/2013WO2013149805A1 Apparatus and method for the transport on a liquid
10/10/2013WO2013149669A1 A method of fabricating a tunnel oxide layer and a tunnel oxide layer for a semiconductor device
10/10/2013WO2013149482A1 New normal-pressure dual radio frequency electrode plasma free radical cleaning spray gun
10/10/2013WO2013149467A1 Array substrate, and manufacturing method thereof and display device
10/10/2013WO2013149463A1 Conductive structure and method for manufacturing same, thin film transistor, array substrate and display device
10/10/2013WO2013149451A1 Quad flat no-lead package component and manufacturing method therefor
10/10/2013WO2013075690A3 Band-to-band tunnelling field effect transistor with graded semiconductor heterostructure in the tunnel junction
10/10/2013US20130267100 Method of manufacturing semiconductor device, substrate processing apparatus and evaporation system
10/10/2013US20130267099 Chemical dispensing system and method
10/10/2013US20130267098 Plasma processing apparatus and plasma processing method
10/10/2013US20130267097 Method and apparatus for forming features with plasma pre-etch treatment on photoresist
10/10/2013US20130267096 Systems for and methods of laser-enhanced plasma processing of semiconductor materials
10/10/2013US20130267095 Method of fabricating and correcting nanoimprint lithography templates
10/10/2013US20130267094 Plasma etching method and plasma processing apparatus
10/10/2013US20130267093 Through Substrate Via Semiconductor Components And Methods of Formation Thereof
10/10/2013US20130267092 Methods of Forming a Fine Pattern on a Substrate and Methods of Forming a Semiconductor Device Having a Fine Pattern
10/10/2013US20130267091 Process to remove Ni and Pt residues for NiPtSi application using Chlorine gas
10/10/2013US20130267090 Method to control metal semiconductor micro-structure
10/10/2013US20130267089 Film for filling through hole interconnects and post processing for interconnect substrates
10/10/2013US20130267088 Method of fabricating semiconductor device
10/10/2013US20130267087 Layout and pad floor plan of power transistor for good performance of spu and stog
10/10/2013US20130267086 Passivating point defects in high-k gate dielectric layers during gate stack formation
10/10/2013US20130267084 Method for forming superactive deactivation-resistant junction with laser anneal and multiple implants
10/10/2013US20130267083 Producing method for semiconductor device
10/10/2013US20130267082 Chalcogenide-containing precursors, methods of making, and methods of using the same for thin film deposition
10/10/2013US20130267081 Post-deposition soft annealing
10/10/2013US20130267080 Method of manufacture for a semiconductor device
10/10/2013US20130267079 Molecular layer deposition of silicon carbide
10/10/2013US20130267078 Processes for preparing stressed semiconductor wafers and for preparing devices including the stressed semiconductor wafers
10/10/2013US20130267077 Method and system for manufacturing semiconductor device
10/10/2013US20130267076 Wafer dicing using hybrid multi-step laser scribing process with plasma etch
10/10/2013US20130267075 Integrated Circuit with Multi Recessed Shallow Trench Isolation
10/10/2013US20130267074 Integration technique using thermal oxide select gate dielectric for select gate and apartial replacement gate for logic
10/10/2013US20130267073 Method of Manufacturing Fin Field Effect Transistor
10/10/2013US20130267072 Non-volatile memory (nvm) and logic integration
10/10/2013US20130267070 Replacement gates to enhance transistor strain
10/10/2013US20130267069 Method of manufacturing a semiconductor device
10/10/2013US20130267068 Processing method of stacked-layer film and manufacturing method of semiconductor device
10/10/2013US20130267065 Method for manufacturing semiconductor device
10/10/2013US20130267063 Method for fabricating a semiconductor device and semiconductor package
10/10/2013US20130267062 Dispensing Tool
10/10/2013US20130267048 Structure and Method for Placement, Sizing and Shaping of Dummy Structures
10/10/2013US20130267047 Topography-Aware Lithography Pattern Check
10/10/2013US20130267046 Method for fabrication of a semiconductor device and structure
10/10/2013US20130267045 Shower head apparatus and method for controllign plasma or gas distribution
10/10/2013US20130267044 Superior integrity of high-k metal gate stacks by preserving a resist material above end caps of gate electrode structures
10/10/2013US20130267042 MRAM Fabrication Method with Sidewall Cleaning
10/10/2013US20130266405 Work piece transfer mechanisms
10/10/2013US20130265690 Electrostatic chuck apparatus
10/10/2013US20130265102 Semiconductor structure and method for manufacturing the same
10/10/2013US20130265031 Nanogap sensor and method of manufacturing the same
10/10/2013US20130264836 Semiconductor Die Collet and Method
10/10/2013US20130264780 Substrate holding apparatus and substrate holding method
10/10/2013US20130264724 Adhesive compound and method for encapsulating an electronic arrangement
10/10/2013US20130264721 Electronic Module
10/10/2013US20130264720 Semiconductor Chips Having Through Silicon Vias and Related Fabrication Methods and Semiconductor Packages
10/10/2013US20130264719 Semiconductor structure and method for manufacturing the same
10/10/2013US20130264717 Multi-level stack having multi-level contact and method
10/10/2013US20130264716 System-In-Package Having Integrated Passive Devices and Method Therefor
10/10/2013US20130264714 Semiconductor device and method of assembling same
10/10/2013US20130264713 Methods of forming conductive structures and methods of forming dram cells
10/10/2013US20130264711 Nanotube electronics templated self-assembly
10/10/2013US20130264709 Semiconductor device, method of manufacturing thereof, circuit board and electronic apparatus
10/10/2013US20130264705 Semiconductor Device and Method of Forming Bump on Substrate to Prevent ELK ILD Delamination During Reflow Process
10/10/2013US20130264701 Integrated cold plate for electronics
10/10/2013US20130264700 Semiconductor device with embedded heat spreading
10/10/2013US20130264698 Semiconductor device with heat dissipation
10/10/2013US20130264696 Semiconductor device
10/10/2013US20130264695 Stacked semiconductor device and method of manufacturing the same
10/10/2013US20130264694 Electronic package structure having exposed lands and method
10/10/2013US20130264693 Lead frame with grooved lead finger
10/10/2013US20130264692 Integrated circuit package and method of forming the same
10/10/2013US20130264691 Integrated circuit and method of manufacturing the same
10/10/2013US20130264690 Method of producing epitaxial wafer and the epitaxial wafer
10/10/2013US20130264688 Method and apparatus providing integrated circuit system with interconnected stacked device wafers
10/10/2013US20130264687 Method for producing columnar structure
10/10/2013US20130264686 Semiconductor wafer processing
10/10/2013US20130264684 Methods and Apparatus of Wafer Level Package for Heterogeneous Integration Technology
10/10/2013US20130264683 Semiconductor structure and manufacturing method of the same
10/10/2013US20130264679 Planar polysilicon regions for precision resistors and electrical fuses and method of fabrication
10/10/2013US20130264678 Method for making a semi-conducting substrate located on an insulation layer
10/10/2013US20130264677 Method for producing an electronic device by assembling semi-conducting blocks and corresponding device
10/10/2013US20130264676 Semiconductor package with through silicon via interconnect and method for fabricating the same
10/10/2013US20130264675 Apparatus for forming memory lines and vias in three dimensional memory arrays using dual damascene process and imprint lithography
10/10/2013US20130264665 Reduction of Capping Layer Resistance Area Product for Magnetic Device Applications
10/10/2013US20130264663 MEMS Device and Method of Making a MEMS Device
10/10/2013US20130264659 Metal Oxide Protective Layer for a Semiconductor Device
10/10/2013US20130264653 Structure and method of high-performance extremely thin silicon on insulator complementary metal-oxide-semiconductor transistors with dual stress buried insulators
10/10/2013US20130264652 Cost-Effective Gate Replacement Process
10/10/2013US20130264646 Diode Biased ESD Protection Device and Method
10/10/2013US20130264643 Method for fabricating a strained structure
10/10/2013US20130264641 Robust isolation for thin-box etsoi mosfets
10/10/2013US20130264640 Drain extended mos transistor having selectively silicided drain
10/10/2013US20130264633 Logic transistor and non-volatile memory cell integration
10/10/2013US20130264631 Vertical nand device with low capacitance and silicided word lines
10/10/2013US20130264629 Nonvolatile memory device and method for fabricating the same
10/10/2013US20130264628 Use of etch process post wordline definition to improve data retention in a flash memory device
10/10/2013US20130264622 Semiconductor circuit structure and process of making the same
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