Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
10/2013
10/03/2013US20130260513 Microelectronic package with terminals on dielectric mass
10/03/2013US20130260512 Method of manufacturing package structure
10/03/2013US20130260511 Lid attach process and apparatus for fabrication of semiconductor packages
10/03/2013US20130260510 3-D Integrated Circuits and Methods of Forming Thereof
10/03/2013US20130260485 Edge triggered calibration
10/03/2013US20130260484 Optimizing light extraction efficiency for an led wafer
10/03/2013US20130260482 Method of manufacturing ferroelectric thin film
10/03/2013US20130260140 Auxiliary sheet for laser dicing
10/03/2013US20130260058 Electronic devices
10/03/2013US20130259610 System and method for gapping conveyed substrates
10/03/2013US20130259457 Heat treatment apparatus for heating substrate by irradiating substrate with flash of light
10/03/2013US20130258759 Methods and Apparatus for SRAM Cell Structure
10/03/2013US20130258756 Vertical transistor, memory cell, device, system and method of forming same
10/03/2013US20130258719 Compound semiconductor device and manufacturing method of the same
10/03/2013US20130258627 Interposer-based damping resistor
10/03/2013US20130258599 Conduction cooling of multi-channel flip chip based panel array circuits
10/03/2013US20130258532 Passive devices for finfet integrated circuit technologies
10/03/2013US20130258265 Array substrate structure and display panel and manufacturing method thereof
10/03/2013US20130257699 Driver circuit, signal processing unit having the driver circuit, method for manufacturing the signal processing unit, and display device
10/03/2013US20130257544 Wireless communication system
10/03/2013US20130257478 Permutable switching network with enhanced interconnectivity for multicasting signals
10/03/2013US20130256964 Wafer suction method, wafer suction stage, and wafer suction system
10/03/2013US20130256922 Method for Fabricating a Semiconductor Device
10/03/2013US20130256915 Packaging substrate, semiconductor package and fabrication method thereof
10/03/2013US20130256914 Package on package structures and methods for forming the same
10/03/2013US20130256913 Die stacking with coupled electrical interconnects to align proximity interconnects
10/03/2013US20130256912 Chip arrangement and a method for forming a chip arrangement
10/03/2013US20130256911 Semiconductor chip stack package and manufacturing method thereof
10/03/2013US20130256910 3d interconnect structure comprising fine pitch single damascene backside metal redistribution lines combined with through-silicon vias
10/03/2013US20130256909 Patterned adhesive tape for backgrinding processes
10/03/2013US20130256908 Inter-die connection within an integrated circuit formed of a stack of circuit dies
10/03/2013US20130256906 Semiconductor device and manufacturing method for the same
10/03/2013US20130256904 Semiconductor device and method for manufacturing the same
10/03/2013US20130256903 Interconnect structure and method for forming the same
10/03/2013US20130256901 Methods for fabricating integrated circuits having substrate contacts and integrated circuits having substrate contacts
10/03/2013US20130256900 Ultrathin buried die module and method of manufacturing thereof
10/03/2013US20130256899 Methods and apparatuses to form self-aligned caps
10/03/2013US20130256896 Vertical mount package and wafer level packaging therefor
10/03/2013US20130256895 Stacked semiconductor components with universal interconnect footprint
10/03/2013US20130256894 Porous Metallic Film as Die Attach and Interconnect
10/03/2013US20130256893 Bonding pad structure with dense via array
10/03/2013US20130256892 Display device and manufacturing method thereof
10/03/2013US20130256891 Semiconductor device with a copper line and method for manufacturing the same
10/03/2013US20130256890 Shallow via formation by oxidation
10/03/2013US20130256889 Substrate and semiconductor device
10/03/2013US20130256888 Interconnect structure and method for forming the same
10/03/2013US20130256884 Grid fan-out wafer level package and methods of manufacturing a grid fan-out wafer level package
10/03/2013US20130256883 Rotated semiconductor device fan-out wafer level packages and methods of manufacturing rotated semiconductor device fan-out wafer level packages
10/03/2013US20130256879 Wiring substrate and method of manufacturing the same, and semiconductor device and method of manufacturing the same
10/03/2013US20130256875 Semiconductor package, package structure and fabrication method thereof
10/03/2013US20130256873 System, method, and computer program product for preparing a substrate post
10/03/2013US20130256872 Thermal management of stacked semiconductor chips with electrically non-functional interconnects
10/03/2013US20130256871 Semiconductor chip device with fragmented solder structure pads
10/03/2013US20130256870 Packaging device and method of making the same
10/03/2013US20130256869 Chip package and manufacturing method thereof
10/03/2013US20130256868 Thermal interface material for semiconductor chip and method for forming the same
10/03/2013US20130256866 Semiconductor Device and Method of Forming Prefabricated Heat Spreader Frame with Embedded Semiconductor Die
10/03/2013US20130256864 Semiconductor package and method of manufacturing the same
10/03/2013US20130256861 Integrated circuit packaging system with routable circuitry and method of manufacture thereof
10/03/2013US20130256860 Semiconductor device and a manufacturing method thereof
10/03/2013US20130256858 PCB Based RF-Power Package Window Frame
10/03/2013US20130256857 Semiconductor Packages and Methods of Formation Thereof
10/03/2013US20130256856 Multichip Power Semiconductor Device
10/03/2013US20130256855 Chip arrangement, a method for forming a chip arrangement, a chip package, a method for forming a chip package
10/03/2013US20130256852 Stacked Semiconductor Package
10/03/2013US20130256851 Method for manufacturing semiconductor device using mold having resin dam and semiconductor device
10/03/2013US20130256847 Semiconductor devices including electromagnetic interference shield
10/03/2013US20130256845 Semiconductor Device and Method for Manufacturing the Same
10/03/2013US20130256843 Wafer sawing method and wafer structure beneficial for performing the same
10/03/2013US20130256841 Via plugs
10/03/2013US20130256838 Method of epitaxial doped germanium tin alloy formation
10/03/2013US20130256836 Package-on-Package (PoP) Device with Integrated Passive Device
10/03/2013US20130256835 Non-planar capacitor and method of forming the non-planar capacitor
10/03/2013US20130256834 Back-side mom/mim devices
10/03/2013US20130256833 Triple well isolated diode and method of making
10/03/2013US20130256830 Semiconductor-on-oxide structure and method of forming
10/03/2013US20130256829 Compound semiconductor device and method of manufacturing the same
10/03/2013US20130256812 Method for reducing interfacial layer thickness for high-k and metal gate stack
10/03/2013US20130256810 Semiconductor Device and Method for Manufacturing the Same
10/03/2013US20130256809 Electrical-free dummy gate
10/03/2013US20130256808 Semiconductor Device and Method of Manufacturing the Same
10/03/2013US20130256806 Semiconductor device including contact holes and method for forming the same
10/03/2013US20130256805 Metal gate semiconductor device and method of fabricating thereof
10/03/2013US20130256804 ROM Arrays Having Memory Cell Transistors Programmed Using Metal Gates
10/03/2013US20130256803 Method of integrating buried threshold voltage adjustment layers for cmos processing
10/03/2013US20130256802 Replacement Gate With Reduced Gate Leakage Current
10/03/2013US20130256801 Integrated circuit structure to resolve deep-well plasma charging problem and method of forming the same
10/03/2013US20130256796 Mosfet with slective dopant deactivation underneath gate
10/03/2013US20130256795 Ldmos with accumulation enhancement implant
10/03/2013US20130256789 Power semiconductor device and fabrication method thereof
10/03/2013US20130256787 Multi-landing contact etching
10/03/2013US20130256786 Trench mosfet with shielded electrode and avalanche enhancement region
10/03/2013US20130256784 MOSFETs with Channels on Nothing and Methods for Forming the Same
10/03/2013US20130256777 Three dimensional floating gate nand memory
10/03/2013US20130256776 Double-gate electronic memory cell and method of manufacturing such a cell
10/03/2013US20130256773 Electrically erasable programmable non-volatile memory
10/03/2013US20130256772 Multiple-Time Programming Memory Cells and Methods for Forming the Same
10/03/2013US20130256767 Source/drain contacts for non-planar transistors
10/03/2013US20130256760 Method for forming group iii/v conformal layers on silicon substrates
10/03/2013US20130256759 Fin Structure for a FinFET Device
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