Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
10/2013
10/23/2013CN101930957B Power semiconductor device package and fabrication method
10/23/2013CN101930945B Preparation method of DMOS (Domplementary Metal Oxide Semiconductor) with self-aligned channel in BCD (Bipolar CMOS DMOS) process
10/23/2013CN101877319B Method of manufacturing flexible display device
10/23/2013CN101872739B Groove filling method
10/23/2013CN101866870B Wafer adsorbing and carrying mechanism for special equipment of semiconductor
10/23/2013CN101794735B Methods of forming contact structures and semiconductor devices fabricated using contact structures
10/23/2013CN101736320B Film deposition apparatus and cleaning method for same
10/23/2013CN101685771B Method for pre-conditioning and stabilizing an etching chamber and method for cleaning etching chamber
10/23/2013CN101684549B Method for manufacturing nitride semiconductor device
10/23/2013CN101661936B Semiconductor device and fabricating method for same
10/23/2013CN101622713B Source/drain stressor and method therefor
10/23/2013CN101615632B Structure and method for forming shielded gate trench FET with inter-electrode dielectric having nitride layer therein
10/23/2013CN101593738B Semiconductor device and method for manufacturing same
10/23/2013CN101589172B High strip rate downstream chamber
10/23/2013CN101571477B Method and apparatus for detecting plasma unconfinement
10/23/2013CN101542684B Device and method for removing liquid from surface of disc-like article
10/23/2013CN101533425B Power supply noise analysis apparatus, method and program for electronic circuit board
10/23/2013CN101451047B Chemico-mechanical polishing liquid
10/23/2013CN101441994B In-line package apparatuses and methods
10/23/2013CN101432867B Methods and materials useful for chip stacking, chip and wafer bonding
10/23/2013CN101416297B Epitaxial silicon germanium for reduced contact resistance in field-effect transistors
10/23/2013CN101414600B Cooling mechanism for stacked die package, and method of manufacturing stacked die package containing same
10/22/2013US8566757 Layout of phase shifting photolithographic masks with refined shifter shapes
10/22/2013US8566435 Computer implemented configuration of a management module
10/22/2013US8565016 System having improved surface planarity for bit material deposition
10/22/2013US8564578 Semiconductor device
10/22/2013US8564143 Overlay mark for multiple pre-layers and currently layer
10/22/2013US8564136 Semiconductor device and method for fabricating the same
10/22/2013US8564131 Semiconductor device and method for manufacturing the same
10/22/2013US8564120 Heat dissipation in temperature critical device areas of semiconductor devices by heat pipes connecting to the substrate backside
10/22/2013US8564107 Lead frame and method for manufacturing the same
10/22/2013US8564106 Wafer level packaging
10/22/2013US8564104 Passivation layer structure of semiconductor device and method for forming the same
10/22/2013US8564103 Method of manufacturing an electronic device
10/22/2013US8564100 Semiconductor device
10/22/2013US8564098 Controlling the recombination rate in a bipolar semiconductor component
10/22/2013US8564095 Capacitors including a rutile titanium dioxide material and semiconductor devices incorporating same
10/22/2013US8564087 Photodiode manufacturing method and photodiodes
10/22/2013US8564084 Radiation detection and a method of manufacturing a radiation detector
10/22/2013US8564079 STT MRAM magnetic tunnel junction architecture and integration
10/22/2013US8564077 Package for electronic component, manufacturing method thereof and sensing apparatus
10/22/2013US8564072 Semiconductor device having a blocking structure and method of manufacturing the same
10/22/2013US8564068 Device and methods for small trench patterning
10/22/2013US8564067 Silicon-on-insulator (SOI) structure configured for reduced harmonics and method of forming the structure
10/22/2013US8564066 Interface-free metal gate stack
10/22/2013US8564064 Controlled fin-merging for fin type FET devices
10/22/2013US8564061 Semiconductor device
10/22/2013US8564056 Semiconductor device with vertical channel over buried bit line
10/22/2013US8564054 Trench semiconductor power device having active cells under gate metal pad
10/22/2013US8564051 Power semiconductor device with buried source electrode
10/22/2013US8564045 Memory arrays having substantially vertical, adjacent semiconductor structures and the formation thereof
10/22/2013US8564044 Non-volatile memory and logic circuit process integration
10/22/2013US8564035 Image sensor and image sensor integrated type active matrix type display device
10/22/2013US8564032 Photo detector device, photo sensor and spectrum sensor
10/22/2013US8564025 Nanowire FET having induced radial strain
10/22/2013US8564018 Relaxed silicon germanium substrate with low defect density
10/22/2013US8564017 Silicon carbide semiconductor device and method for manufacturing same
10/22/2013US8564001 Organic light emitting device lighting panel
10/22/2013US8563993 Display device and fabrication method for display device
10/22/2013US8563988 Semiconductor element and manufacturing method therefor
10/22/2013US8563987 Semiconductor device and method for fabricating the device
10/22/2013US8563986 Power semiconductor devices having selectively doped JFET regions and related methods of forming such devices
10/22/2013US8563983 Display panel, display device, and method manufacturing same
10/22/2013US8563979 Method for producing display device
10/22/2013US8563966 Nano metal particles based tunneling field effect transistor and nano-switch
10/22/2013US8563965 Doped graphene electronic materials
10/22/2013US8563963 Light-emitting diode die packages and methods for producing same
10/22/2013US8563960 Phase change random access memory and method for manufacturing the same
10/22/2013US8563893 Laser material processing system
10/22/2013US8563846 Thin film type solar cell and method for manufacturing the same
10/22/2013US8563445 Conformal layers by radical-component CVD
10/22/2013US8563444 ALD of metal silicate films
10/22/2013US8563443 Method of depositing dielectric film by ALD using precursor containing silicon, hydrocarbon, and halogen
10/22/2013US8563442 Method for manufacturing nitrogen compound semiconductor substrate and nitrogen compound semiconductor substrate, and method for manufacturing single crystal SiC substrate and single crystal SiC substrate
10/22/2013US8563441 Methods for fabricating memory cells having fin structures with smooth sidewalls and rounded top corners and edges
10/22/2013US8563440 Method for chemically treating a substrate
10/22/2013US8563439 Method of pitch dimension shrinkage
10/22/2013US8563438 Method for manufacturing semiconductor device
10/22/2013US8563437 Method for treating group III nitride semiconductor
10/22/2013US8563436 Chemical mechanical polishing composition and methods relating thereto
10/22/2013US8563435 Method of reducing damage to an electron beam inspected semiconductor substrate, and methods of inspecting a semiconductor substrate
10/22/2013US8563434 Semiconductor device contacts
10/22/2013US8563433 Process to form via hole in semiconductor wafer
10/22/2013US8563432 Method for forming through silicon via structure
10/22/2013US8563431 Method for manufacturing semiconductor device
10/22/2013US8563430 Semiconductor integrated circuit and method for fabricating the same
10/22/2013US8563429 Methods of forming a metal silicide layer for semiconductor devices
10/22/2013US8563428 Methods for depositing metal in high aspect ratio features
10/22/2013US8563426 Shrinkage of contact elements and vias in a semiconductor device by incorporating additional tapering material
10/22/2013US8563425 Selective local interconnect to gate in a self aligned local interconnect process
10/22/2013US8563424 Process for forming cobalt and cobalt silicide materials in tungsten contact applications
10/22/2013US8563423 Fluorine depleted adhesion layer for metal interconnect structure
10/22/2013US8563421 Method of fabricating semiconductor device
10/22/2013US8563420 Multilayer printed wiring board
10/22/2013US8563419 Method of manufacturing an interconnect structure and design structure thereof
10/22/2013US8563418 Semiconductor device and method of forming vertically offset bond on trace interconnects on different height traces
10/22/2013US8563417 Method for packaging ultra-thin chip with solder ball thermo-compression in wafer level packaging process
10/22/2013US8563416 Coaxial solder bump support structure
10/22/2013US8563415 Semiconductor device and method of manufacturing the same
10/22/2013US8563413 Semiconductor device with buried gate and method for fabricating the same