Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
10/2003
10/07/2003US6630984 Lithographic apparatus, device manufacturing method, and device manufactured thereby
10/07/2003US6630977 Semiconductor device with capacitor formed around contact hole
10/07/2003US6630850 Semiconductor integrated circuit including command decoder for receiving control signals
10/07/2003US6630839 Contactor, a method of manufacturing the contactor and a device and method of testing electronic component using the contactor
10/07/2003US6630792 High frequency power source, plasma processing apparatus, inspection method for plasma processing apparatus, and plasma processing method
10/07/2003US6630772 Device comprising carbon nanotube field emitter structure and process for forming device
10/07/2003US6630743 Copper plated PTH barrels and methods for fabricating
10/07/2003US6630742 Method for forming bumps, semiconductor device, and solder paste
10/07/2003US6630741 Method of reducing electromigration by ordering zinc-doping in an electroplated copper-zinc interconnect and a semiconductor device thereby formed
10/07/2003US6630740 Semiconductor device
10/07/2003US6630739 Planarization structure and method for dielectric layers
10/07/2003US6630735 Insulator/metal bonding island for active-area silver epoxy bonding
10/07/2003US6630728 Plastic integrated circuit package and leadframe for making the package
10/07/2003US6630725 Electronic component and method of manufacture
10/07/2003US6630723 Laser adjustment or laser programming of laser fuses of an integrated circuit on a chip, with laser light, the integrated circuit having a plurality of laser fuses and being connected to a plurality of contact pads on the chip, and the
10/07/2003US6630721 Polysilicon sidewall with silicide formation to produce high performance MOSFETS
10/07/2003US6630720 Asymmetric semiconductor device having dual work function gate and method of fabrication
10/07/2003US6630718 Transistor gate and local interconnect
10/07/2003US6630717 CMOS semiconductor circuit with reverse bias applied for reduced power consumption
10/07/2003US6630716 Disposable spacer
10/07/2003US6630715 Asymmetrical MOSFET layout for high currents and high speed operation
10/07/2003US6630714 Semiconductor device formed in semiconductor layer arranged on substrate with one of insulating film and cavity interposed between the substrate and the semiconductor layer
10/07/2003US6630713 Low temperature silicon wafer bond process with bulk material bond strength
10/07/2003US6630712 Transistor with dynamic source/drain extensions
10/07/2003US6630711 Semiconductor structures with trench contacts
10/07/2003US6630710 Semiconductor device (e.g., MOSFET) having a channel above the surface of the wafer containing a well and a junction. The elevated channel may be selectively epitaxially grown and enables higher mobility, enabling a higher current flow at
10/07/2003US6630709 Multi-level flash EEPROM cell and method of manufacture thereof
10/07/2003US6630708 Non-volatile memory and method for fabricating the same
10/07/2003US6630707 Semiconductor device including logic circuit and memory circuit
10/07/2003US6630706 Localized array threshold voltage implant to enhance charge storage within DRAM memory cells
10/07/2003US6630705 Semiconductor device with capacitor electrodes
10/07/2003US6630704 Semiconductor device
10/07/2003US6630703 Magnetoresistive memory cell configuration and method for its production
10/07/2003US6630702 Method of using titanium doped aluminum oxide for passivation of ferroelectric materials and devices including the same
10/07/2003US6630701 Signal to noise ratio is disclosed. The buried channel CMOS imager provides reduced noise by keeping collected charge away from the surface of the substrate, thereby improving charge loss to the substrate.
10/07/2003US6630700 NMOS circuit in isolated wells that are connected by a bias stack having pluralirty of diode elements
10/07/2003US6630699 Transistor device having an isolation structure located under a source region, drain region and channel region and a method of manufacture thereof
10/07/2003US6630698 High-voltage semiconductor component
10/07/2003US6630696 Silica zeolite low-k dielectric thin films
10/07/2003US6630695 InGaN/AlGaN/GaN multilayer buffer for growth of GaN on sapphire
10/07/2003US6630692 III-Nitride light emitting devices with low driving voltage
10/07/2003US6630690 Optoelectronic device with a Group III Nitride active layer is disclosed that comprises a silicon carbide substrate; an optoelectronic diode with a Group III nitride active layer; a buffer structure selected from the group consisting of gallium
10/07/2003US6630689 Semiconductor LED flip-chip with high reflectivity dielectric coating on the mesa
10/07/2003US6630688 Contact structures of wirings and methods for manufacturing the same, and thin film transistor array panels including the same and methods for manufacturing the same
10/07/2003US6630687 Active matrix display device having wiring layers which are connected over multiple contact parts
10/07/2003US6630643 Method and structure for forming metallic interconnections using directed thermal diffusion
10/07/2003US6630520 Composition containing a cross-linkable matrix precursor and a poragen, and a porous matrix prepared therefrom
10/07/2003US6630433 Oxidizing reactant selected from ammonium persulfate, hydrogen peroxide, nitric acid, co-reactant selected from phosphoric acid, sulfuric acid, nitric acid, oxalic acid, acetic acid, organic acids, additives
10/07/2003US6630413 CVD syntheses of silicon nitride materials
10/07/2003US6630412 Multilayer structure containing dielectric; overcoating copper wires
10/07/2003US6630410 Self-aligned PECVD etch mask
10/07/2003US6630409 Method of forming a polycide electrode in a semiconductor device
10/07/2003US6630408 Self alignment process to fabricate attenuated shifting mask with chrome border
10/07/2003US6630407 Plasma etching of organic antireflective coating
10/07/2003US6630406 Plasma ashing process
10/07/2003US6630405 Method of gate patterning for sub-0.1 μm technology
10/07/2003US6630404 Reducing feature dimension using self-assembled monolayer
10/07/2003US6630402 Integrated circuit resistant to the formation of cracks in a passivation layer
10/07/2003US6630401 Radical-assisted sequential CVD
10/07/2003US6630400 Method for electroless plating a contact pad
10/07/2003US6630399 Titanium disilicide resistance in pinched active regions of semiconductor devices
10/07/2003US6630398 Borderless contact with buffer layer
10/07/2003US6630397 Method to improve surface uniformity of a layer of arc used for the creation of contact plugs
10/07/2003US6630396 Use of a silicon carbide adhesion promoter layer to enhance the adhesion of silicon nitride to low-k fluorinated amorphous carbon
10/07/2003US6630395 Methods for fabricating electrical connections to semiconductor structures incorporating low-k dielectric materials
10/07/2003US6630394 System for reducing silicon-consumption through selective deposition
10/07/2003US6630393 Semiconductor device manufacturing method and semiconductor device manufacturing by the same method
10/07/2003US6630392 Method for fabricating flash memory device
10/07/2003US6630391 Boron incorporated diffusion barrier material
10/07/2003US6630390 Method of forming a semiconductor device using a carbon doped oxide layer to control the chemical mechanical polishing of a dielectric layer
10/07/2003US6630389 Method for manufacturing semiconductor device
10/07/2003US6630388 Double-gate field-effect transistor, integrated circuit using the transistor and method of manufacturing the same
10/07/2003US6630387 Method for forming capacitor of semiconductor memory device using electroplating method
10/07/2003US6630386 CMOS manufacturing process with self-amorphized source/drain junctions and extensions
10/07/2003US6630385 MOSFET with differential halo implant and annealing strategy
10/07/2003US6630384 Method of fabricating double densed core gates in sonos flash memory
10/07/2003US6630383 Bi-layer floating gate for improved work function between floating gate and a high-K dielectric layer
10/07/2003US6630382 Current controlled field effect transistor
10/07/2003US6630381 Preventing dielectric thickening over a floating gate area of a transistor
10/07/2003US6630380 Method for making three-dimensional metal-insulator-metal capacitors for dynamic random access memory (DRAM) and ferroelectric random access memory (FERAM)
10/07/2003US6630379 Method of manufacturing 6F2 trench capacitor DRAM cell having vertical MOSFET and 3F bitline pitch
10/07/2003US6630378 Method of fabricating a dynamic random access memory device having stacked capacitor memory cell arrays
10/07/2003US6630377 Method for making high-gain vertical bipolar junction transistor structures compatible with CMOS process
10/07/2003US6630376 Body-tied-to-body SOI CMOS inverter circuit
10/07/2003US6630375 Process for manufacturing a semiconductor wafer, a semiconductor wafer, process for manufacturing a semiconductor integrated circuit device, and semiconductor integrated circuit device
10/07/2003US6630374 Resin sealing method and resin sealing apparatus
10/07/2003US6630371 Chip on board and heat sink attachment methods
10/07/2003US6630369 Sample preparation apparatus and method
10/07/2003US6630368 Substrate for mounting a semiconductor chip and method for manufacturing a semiconductor device
10/07/2003US6630365 Stereolithographic method and apparatus for fabricating spacers for semiconductor devices and resulting structures
10/07/2003US6630363 Method for evaluating impurity concentrations in unpolished wafers grown by the Czochralski method
10/07/2003US6630362 Method and apparatus for performing trench depth analysis
10/07/2003US6630361 Use of scatterometry for in-situ control of gaseous phase chemical trim process
10/07/2003US6630360 Advanced process control (APC) of copper thickness for chemical mechanical planarization (CMP) optimization
10/07/2003US6630308 Generating preferential amino acid sequences on substrate; obtain substrate, deblock, expose to amino acids, recover preferential particles
10/07/2003US6630288 Trimming the feature patterned on the photoresist layer to form a trimmed feature, where a vertical trim rate and a lateral trim rate are associated with the feature and the vertical trim rate is slower than that of the lateral
10/07/2003US6630280 Positive photoresist composition
10/07/2003US6630279 Positive photoresist composition
10/07/2003US6630203 Electroless process for the preparation of particle enhanced electric contact surfaces
10/07/2003US6630201 Providing gas in chamber for reacting with a surface of a substrate; retaining substrate on an electrostatic chuck (ESC) assembly by electrostatic attraction, supplying a DC bias voltage to electrodes to couple a DC bias voltage
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