Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
02/2004
02/24/2004US6698002 Blocked based design methodology
02/24/2004US6698000 Semiconductor process parameter determining method, semiconductor process parameter determining system, and semiconductor process parameter determining program
02/24/2004US6697771 Semiconductor device manufacturing system and the method thereof
02/24/2004US6697698 Overlay inspection apparatus for semiconductor substrate and method thereof
02/24/2004US6697697 Effective channel length control using ion implant feed forward
02/24/2004US6697695 Laser device management system
02/24/2004US6697691 Method and apparatus for fault model analysis in manufacturing tools
02/24/2004US6697621 Method and apparatus for providing services in a private wireless network
02/24/2004US6697517 Particle detection and embedded vision system to enhance substrate yield and throughput
02/24/2004US6697412 Long wavelength laser diodes on metamorphic buffer modified gallium arsenide wafers
02/24/2004US6697407 Semiconductor laser attaining high efficiency and high power, and method of manufacturing the same
02/24/2004US6697278 Semiconductor memory device
02/24/2004US6697261 Multileveled printed circuit board unit including substrate interposed between stacked bumps
02/24/2004US6697199 Objective with lenses made of a crystalline material
02/24/2004US6697194 Antireflection coating for ultraviolet light at large angles of incidence
02/24/2004US6697153 Method and apparatus for analyzing line structures
02/24/2004US6697145 Substrate processing apparatus for coating photoresist on a substrate and forming a predetermined pattern on a substrate by exposure
02/24/2004US6697096 Laser beam pattern generator having rotating scanner compensator and method
02/24/2004US6696916 Integrated vertical resistor structure with reduced dimensions, for high voltage, and manufacturing process thereof
02/24/2004US6696880 High voltage switch suitable for non-volatile memories
02/24/2004US6696867 Voltage generator with stability indicator circuit
02/24/2004US6696863 Clock signal distribution circuit
02/24/2004US6696849 Fabrication method of semiconductor integrated circuit device and its testing apparatus
02/24/2004US6696764 Multilayer thin film wirings formed on front and back surfaces of metal/alloy, then cut to expose inner electrode pads on which chips are mounted
02/24/2004US6696762 Bi-level digit line architecture for high density DRAMS
02/24/2004US6696761 Method to encapsulate copper plug for interconnect metallization
02/24/2004US6696760 Semiconductor structure
02/24/2004US6696759 Together, the diamond or diamond-like carbon polish-stop layer and the protective layer are used as a hard-mask for patterning the trenches that will become the metal features
02/24/2004US6696758 Interconnect structures and a method of electroless introduction of interconnect structures
02/24/2004US6696756 Gold wire for use in semiconductor packaging and high-frequency signal transmission
02/24/2004US6696752 Encapsulated semiconductor device with flash-proof structure
02/24/2004US6696748 Stress balanced semiconductor packages, method of fabrication and modified mold segment
02/24/2004US6696746 Buried conductors
02/24/2004US6696745 Methods for use in forming a capacitor and structures resulting from same
02/24/2004US6696743 Semiconductor transistor having gate electrode and/or gate wiring
02/24/2004US6696742 Semiconductor memory device
02/24/2004US6696741 High breakdown voltage PN junction structure, and related manufacturing process
02/24/2004US6696739 Minimizing shading loss; lower cost
02/24/2004US6696738 Having photosensitive chip disposed within chamber connected in flip chip manner; metal sheets and frame layer formed integrally without traces
02/24/2004US6696735 Semiconductor device and method for fabricating the same
02/24/2004US6696734 LDD high voltage MOS transistor
02/24/2004US6696733 Semiconductor devices including electrode structure
02/24/2004US6696732 Semiconductor device having S/D to S/D connection and isolation region between two semiconductor elements
02/24/2004US6696730 Electrostatic discharge protection device for semiconductor integrated circuit, method for producing the same, and electrostatic discharge protection circuit using the same
02/24/2004US6696729 Semiconductor device having diffusion regions with different junction depths
02/24/2004US6696727 Field effect transistor having improved withstand voltage
02/24/2004US6696726 Vertical MOSFET with ultra-low resistance and low gate charge
02/24/2004US6696725 Dual-gate MOSFET with channel potential engineering
02/24/2004US6696724 Having nonvolatile memory cells more compact than planar ones
02/24/2004US6696723 Electrically erasable, programmable, non-volatile memory device compatible with a CMOS/SOI production process
02/24/2004US6696722 Storage node of DRAM cell
02/24/2004US6696721 Semiconductor device having a three-dimensional capacitor such as a stack-type capacitor
02/24/2004US6696720 Semiconductor device having stacked capacitor and protection element
02/24/2004US6696719 Semiconductor device with improved peripheral resistance element and method for fabricating same
02/24/2004US6696718 Capacitor having an electrode formed from a transition metal or a conductive metal-oxide, and method of forming same
02/24/2004US6696717 Memory cell with vertical transistor and trench capacitor
02/24/2004US6696716 Structures and methods for enhancing capacitors in integrated ciruits
02/24/2004US6696715 Method and structure for reducing leakage current in capacitors
02/24/2004US6696713 Semiconductor memory provided with vertical transistor and method of manufacturing the same
02/24/2004US6696711 Semiconductor device and power amplifier using the same
02/24/2004US6696710 Heterojunction bipolar transistor (HBT) having an improved emitter-base junction
02/24/2004US6696708 Electrostatic discharge protection apparatus
02/24/2004US6696707 High voltage integrated switching devices on a bonded and trenched silicon substrate
02/24/2004US6696706 Structure and method for a junction field effect transistor with reduced gate capacitance
02/24/2004US6696705 Power semiconductor component having a mesa edge termination
02/24/2004US6696702 Silicon carbide semiconductor switching device
02/24/2004US6696701 Electrostatic discharge protection for pixellated electronic device
02/24/2004US6696688 Apparatus for magnetically scanning and/or switching a charged-particle beam
02/24/2004US6696679 Method for focusing of disk-shaped objects with patterned surfaces during imaging
02/24/2004US6696669 Circuit and method for heating an adhesive to package or rework a semiconductor die
02/24/2004US6696663 Inductively coupled plasma apparatus
02/24/2004US6696644 Polymer-embedded solder bumps for reliable plastic package attachment
02/24/2004US6696538 High density; heat resistance; polysilicates
02/24/2004US6696372 Method of fabricating a semiconductor structure having quantum wires and a semiconductor device including such structure
02/24/2004US6696368 Titanium boronitride layer for high aspect ratio semiconductor devices
02/24/2004US6696367 System for the improved handling of wafers within a process tool
02/24/2004US6696366 Technique for etching a low capacitance dielectric layer
02/24/2004US6696365 Process for in-situ etching a hardmask stack
02/24/2004US6696363 Method of and apparatus for substrate pre-treatment
02/24/2004US6696362 Method for using an in situ particle sensor for monitoring particle performance in plasma deposition processes
02/24/2004US6696361 Post-CMP removal of surface contaminants from silicon wafer
02/24/2004US6696360 Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow
02/24/2004US6696359 Design layout method for metal lines of an integrated circuit
02/24/2004US6696358 Viscous protective overlayers for planarization of integrated circuits
02/24/2004US6696357 Method for manufacturing semiconductor integrated circuit devices using a conductive layer to prevent peeling between a bonding pad and an underlying insulating film
02/24/2004US6696356 Method of making a bump on a substrate without ribbon residue
02/24/2004US6696354 Method of forming salicide
02/24/2004US6696353 Integrated circuit chip having anti-moisture-absorption film at edge thereof and method of forming anti-moisture-absorption film
02/24/2004US6696352 Method of manufacture of a multi-layered substrate with a thin single crystalline layer and a versatile sacrificial layer
02/24/2004US6696351 Semiconductor device having a selectively deposited conductive layer
02/24/2004US6696350 Method of fabricating memory device
02/24/2004US6696349 STI leakage reduction
02/24/2004US6696348 Wide neck shallow trench isolation region to prevent strain relaxation at shallow trench isolation region edges
02/24/2004US6696347 Production process for semiconductor device
02/24/2004US6696346 Method of manufacturing semiconductor device
02/24/2004US6696345 Metal-gate electrode for CMOS transistor applications
02/24/2004US6696344 Method for forming a bottle-shaped trench
02/24/2004US6696342 Small emitter and base-collector bi-polar transistor
02/24/2004US6696340 Semiconductor devices having a non-volatile memory transistor and methods for manufacturing the same
02/24/2004US6696339 Dual-damascene bit line structures for microelectronic devices and methods of fabricating microelectronic devices