Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
11/2013
11/28/2013US20130316540 Method for removing oxide
11/28/2013US20130316539 Method for reducing morphological difference between n-doped and undoped polysilicon gates after etching
11/28/2013US20130316538 Surface morphology generation and transfer by spalling
11/28/2013US20130316537 Self-aligned nand flash select-gate wordlines for spacer double patterning
11/28/2013US20130316536 Semiconductor manufacturing device and semiconductor device manufacturing method
11/28/2013US20130316535 Methods of forming semiconductor devices with metal silicide using pre-amorphization implants and devices so formed
11/28/2013US20130316534 Fabrication method for circuit substrate having post-fed die side power supply connections
11/28/2013US20130316533 Method for removing native oxide and associated residue from a substrate
11/28/2013US20130316532 Method of manufacturing a tungsten plug
11/28/2013US20130316531 Method for forming metal wire
11/28/2013US20130316530 Three-Dimensional Semiconductor Architecture
11/28/2013US20130316529 Method of forming a micro device transfer head with silicon electrode
11/28/2013US20130316528 Interconnect Barrier Structure and Method
11/28/2013US20130316527 Multi-Chip-Scale Package
11/28/2013US20130316525 Semiconductor device having selectively nitrided gate insulating layer and method of fabricating the same
11/28/2013US20130316523 Method of manufacturing a semiconductor device
11/28/2013US20130316522 Method for manufacturing soi wafer
11/28/2013US20130316521 Method for producing silicon wafer
11/28/2013US20130316520 Methods of forming contact regions using sacrificial layers
11/28/2013US20130316519 Techniques for Forming a Chalcogenide Thin Film Using Additive to a Liquid-Based Chalcogenide Precursor
11/28/2013US20130316518 Pecvd deposition of smooth silicon films
11/28/2013US20130316517 Substrate dividing method
11/28/2013US20130316516 Bonding system and bonding method
11/28/2013US20130316515 Method for producing silicon dioxide film
11/28/2013US20130316514 Method of fabricating a gate
11/28/2013US20130316513 Fin isolation for multigate transistors
11/28/2013US20130316511 Superior stability of characteristics of transistors having an early formed high-k metal gate
11/28/2013US20130316510 Method of forming a resist pattern with multiple post exposure baking steps
11/28/2013US20130316509 Semiconductor Device Manufacturing Method
11/28/2013US20130316506 Semiconductor process
11/28/2013US20130316503 STRUCTURE AND METHOD TO MODULATE THRESHOLD VOLTAGE FOR HIGH-K METAL GATE FIELD EFFECT TRANSISTORS (FETs)
11/28/2013US20130316501 Ultra-thin near-hermetic package based on rainier
11/28/2013US20130316499 Chip package and fabrication method thereof
11/28/2013US20130316497 Three dimensional microelectronic components and fabrication methods for same
11/28/2013US20130316495 Substrate for semiconductor package and method of manufacturing thereof
11/28/2013US20130316493 Method for manufacturing semiconductor device
11/28/2013US20130316488 Removal of stressor layer from a spalled layer and method of making a bifacial solar cell using the same
11/28/2013US20130316482 In Situ Synthesis of Nanoparticles on Substrates by Inkjet Printing
11/28/2013US20130316472 High productivity combinatorial oxide terracing and pvd/ald metal deposition combined with lithography for gate work function extraction
11/28/2013US20130316471 Test Line Placement to Improve Die Sawing Quality
11/28/2013US20130316470 Method which can form contact holes in wafer of semiconductor
11/28/2013US20130316139 Method for manufacturing silicon substrate and silicon substrate
11/28/2013US20130316073 Method Of Forming An Interconnect Structure Having An Enlarged Region
11/28/2013US20130315576 Heat treatment apparatus and heat treatment method for measuring particle concentration
11/28/2013US20130315004 Semiconductor device, a method for manufacturing the same, and a system having the same
11/28/2013US20130314986 Thyristors
11/28/2013US20130314710 Methods and Systems for Determining a Critical Dimension and Overlay of a Specimen
11/28/2013US20130314687 Transverse electric-field type liquid crystal display device, process of manufacturing the same, and scan-exposing device
11/28/2013US20130314146 Binary control arrangement and method of making and using the same
11/28/2013US20130313727 Multi-stacked bbul package
11/28/2013US20130313726 Low-temperature flip chip die attach
11/28/2013US20130313724 Shielded coplanar line
11/28/2013US20130313720 Packaging substrate with reliable via structure
11/28/2013US20130313719 Chip packages and methods for manufacturing a chip package
11/28/2013US20130313718 Substrates Comprising Integrated Circuitry, Methods Of Processing A Substrate Comprising Integrated Circuitry, And Methods Of Back-Side Thinning A Substrate Comprising Integrated Circuitry
11/28/2013US20130313717 Spacer for enhancing via pattern overlay tolerence
11/28/2013US20130313716 Substrate-less stackable package with wire-bond interconnect
11/28/2013US20130313712 Multi-Chip Package and Method of Manufacturing Thereof
11/28/2013US20130313711 Semiconductor Device And A Method Of Manufacturing Same
11/28/2013US20130313710 Semiconductor Constructions and Methods of Forming Semiconductor Constructions
11/28/2013US20130313705 Implementing decoupling devices inside a tsv dram stack
11/28/2013US20130313702 Semiconductor device and method for manufacturing the same
11/28/2013US20130313700 Cavity-type semiconductor package and method of packaging same
11/28/2013US20130313699 Fan-out high-density packaging methods and structures
11/28/2013US20130313696 Power semiconductor package and method of manufacturing the same
11/28/2013US20130313691 Thinned wafer and fabricating method thereof
11/28/2013US20130313688 Semiconductor device and method of producing semiconductor device
11/28/2013US20130313687 Through via/the buried via elrctrolde material and the said via structure and the said via manufacturing method
11/28/2013US20130313686 Method for manufacturing semiconductor device, epitaxial substrate for use therein and semi-finished semiconductor device
11/28/2013US20130313685 Carbon material and method of manufacturing the same
11/28/2013US20130313684 Process for forming a planar diode using one mask
11/28/2013US20130313682 Isolated Through Silicon Via and Isolated Deep Silicon Via Having Total or Partial Isolation
11/28/2013US20130313678 Memory Cells And Methods Of Forming Memory Cells
11/28/2013US20130313664 Resistive memory device and fabrication method thereof
11/28/2013US20130313661 Method for Processing a Wafer at Unmasked Areas and Previously Masked Areas to Reduce a Wafer Thickness
11/28/2013US20130313658 High-k dielectric layer based semiconductor structures and fabrication process thereof
11/28/2013US20130313657 Methods of forming fluorinated hafnium oxide gate dielectrics by atomic layer deposition
11/28/2013US20130313656 Methods of atomic layer deposition of hafnium oxide / erbium oxide bi-layer as advanced gate dielectrics
11/28/2013US20130313651 Integrated circuit with on chip planar diode and cmos devices
11/28/2013US20130313648 Semiconductor device having metal gate and manufacturing method thereof
11/28/2013US20130313647 Forming facet-less epitaxy with a cut mask
11/28/2013US20130313645 Semiconductor element and display device using the same
11/28/2013US20130313643 Structure and Method to Modulate Threshold Voltage For High-K Metal Gate Field Effect Transistors (FETs)
11/28/2013US20130313640 Semiconductor Device and Method of Forming Junction Enhanced Trench Power Mosfet
11/28/2013US20130313638 Semiconductor device and manufacturing method thereof
11/28/2013US20130313637 Transistor and method of manufacturing the same
11/28/2013US20130313636 Termination arrangement for vertical mosfet
11/28/2013US20130313633 Semiconductor Device and Method of Forming Junction Enhanced Trench Power Mosfet having Gate Structure Embedded within Trench
11/28/2013US20130313630 Semiconductor integrated circuit device and a method of manufacturing the same
11/28/2013US20130313628 Sonos structure, manufacturing method thereof and semiconductor with the same structure
11/28/2013US20130313627 Multi-Level Contact to a 3D Memory Array and Method of Making
11/28/2013US20130313626 Methods and Apparatus for Non-Volatile Memory Cells
11/28/2013US20130313625 Semiconductor device and method of fabricating the same
11/28/2013US20130313624 Semiconductor device and method for manufacturing semiconductor device
11/28/2013US20130313620 Method and structure for radiation hardening a semiconductor device
11/28/2013US20130313614 METAL SILICIDE SELF-ALIGNED SiGe HETEROJUNCTION BIPOLAR TRANSISTOR AND METHOD OF FORMING THE SAME
11/28/2013US20130313612 HEMT GaN DEVICE WITH A NON-UNIFORM LATERAL TWO DIMENSIONAL ELECTRON GAS PROFILE AND METHOD OF MANUFACTURING THE SAME
11/28/2013US20130313611 A non-uniform lateral profile of two-dimensional electron gas charge density in type iii nitride hemt devices using ion implantation through gray scale mask
11/28/2013US20130313610 Semiconductor device having a necked semiconductor body and method of forming semiconductor bodies of varying width
11/28/2013US20130313579 Dilute sn-doped ge alloys
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