Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
06/2005
06/16/2005US20050130378 Method of integrating high voltage metal oxide semiconductor devices and submicron metal oxide semiconductor devices
06/16/2005US20050130377 Method for processing a semiconductor device comprising a silicon-oxy-nitride dielectric layer
06/16/2005US20050130376 Method for manufacturing flash device
06/16/2005US20050130375 Method of manufacturing flash memory device
06/16/2005US20050130374 Methods for contacting conducting layers overlying magnetoelectronic elements of MRAM devices
06/16/2005US20050130373 Floating trap type nonvolatile memory device and method of fabricating the same
06/16/2005US20050130372 Method for manufacturing flash memory device
06/16/2005US20050130371 Method of fabricating semiconductor device having capacitor
06/16/2005US20050130370 Method for the production of a semiconductor substrate comprising a plurality of gate stacks on a semiconductor substrate, and corresponding semiconductor structure
06/16/2005US20050130369 Semiconductor device having metal-insulator-metal capacitor and method for fabricating the same
06/16/2005US20050130368 Capacitor and manufacturing method thereof, semiconductor device and substrate for a semiconductor device
06/16/2005US20050130367 Method of fabricating semiconductor device by exposing upper sidewalls of contact plug to form charge storage electrode
06/16/2005US20050130366 NiSi metal gate stacks using a boron-trap
06/16/2005US20050130365 Method of manufacturing semi conductor device
06/16/2005US20050130364 Structure and method for ultra-small grain size polysilicon
06/16/2005US20050130363 Method and an apparatus for a hard-coded bit value changeable in any layer of metal
06/16/2005US20050130362 Electronic assembly including a die having an integrated circuit and a layer of diamond to transfer heat
06/16/2005US20050130361 Method to reduce junction leakage current in strained silicon on silicon-germanium devices
06/16/2005US20050130360 Piezo-TFT cantilever MEMS
06/16/2005US20050130359 Method and apparatus for elimination of excessive field oxide recess for thin Si SOI
06/16/2005US20050130358 Strained finFETs and method of manufacture
06/16/2005US20050130357 Method for manufacturing a thin film transistor using poly silicon
06/16/2005US20050130355 Method for manufacturing semiconductor device
06/16/2005US20050130354 Metal oxide semiconductor (MOS) transistor including a planarized material layer and method of fabricating the same
06/16/2005US20050130353 Method of fabricating liquid crystal display panel
06/16/2005US20050130352 High density DRAM with reduced peripheral device area and method of manufacture
06/16/2005US20050130351 Methods for maskless lithography
06/16/2005US20050130350 Flip clip attach and copper clip attach on MOSFET device
06/16/2005US20050130349 Electronic parts built-in substrate and method of manufacturing the same
06/16/2005US20050130345 Castellation wafer level packaging of integrated circuit chips
06/16/2005US20050130344 Method of manufacturing thin film element, thin film transistor circuit substrate, active matrix display device, electro-optical device, and electronic apparatus
06/16/2005US20050130343 Method of making a microelectronic assembly
06/16/2005US20050130342 Method and apparatus for manufacturing a transistor -outline (TO) can having a ceramic header
06/16/2005US20050130337 Sacrificial protective layer for image sensors and method of using
06/16/2005US20050130335 Method of manufacturing master of optical information recording medium, method of manufacturing stamper of optical information recording medium, master and stamper of an optical information recording medium, and optical information recording medium
06/16/2005US20050130334 Self-aligned contact process implementing bias compensation etch endpoint detection and methods for implementing the same
06/16/2005US20050130333 Die sorting apparatus and method
06/16/2005US20050130332 Method for manufacturing semiconductor device
06/16/2005US20050130331 Dual function array feature for cmp process control and inspection
06/16/2005US20050130330 Method for etch processing with end point detection thereof
06/16/2005US20050130329 Method for the prediction of the source of semiconductor part deviations
06/16/2005US20050130328 Method of making a haze free, lead rich PZT film
06/16/2005US20050130326 Method for fabricating capacitor in semiconductor device
06/16/2005US20050130292 Smart disposable plastic lab-on-a-chip for point-of-care testing
06/16/2005US20050130258 Nucleotide sequences coding heat shock protein which self-assembles into regular double-ring structures for use as component of multi-dimensional addressable arrays
06/16/2005US20050130226 Fully integrated protein lab-on-a-chip with smart microfluidics for spot array generation
06/16/2005US20050130082 Hexamethylene diamine tetramethylene phosphonic acid chelating agent; citric acid chelating assistant; developer with calcium chloride; photoresist is a phenolic resin
06/16/2005US20050130079 Overcoating substrate with photoresist ; exposure to hydrophilic compound; exposure to light; development
06/16/2005US20050130076 Method for producing a hard mask in a capacitor device and a hard mask for use in a capacitor device
06/16/2005US20050130074 Method for the manufacture of micro structures
06/16/2005US20050130071 Method for fabricating image sensor with inorganic microlens
06/16/2005US20050130069 Silicon as an etching resistance improving component is contained in the upper-layer resist film of polysiloxane based resin or polyhydroxystyrene based resin but not in the lower-layer resist film;
06/16/2005US20050130068 Resist pattern on a substrate; hydrophilic and hydrophobic processing, causing crosslinking at the interface of the first resist pattern and the resist film and the first resist pattern; and etching the substrate using the second resist pattern as a mask
06/16/2005US20050130067 Pattern formation method
06/16/2005US20050130066 Using a tilted mask layer as a mask to form a selective deposited oxide layer on the sidewall of an opening on the substrate
06/16/2005US20050130056 Polymer compound, resist composition and dissolution inhibitor agent containing the polymer compound
06/16/2005US20050130055 Method and removing resist pattern
06/16/2005US20050130021 Overcoating semiconductor wafer; etching channels in wafer; ion exchange resins; barrier dividing channels; supplying hydrogen and oxidizer with catalyst; forming water
06/16/2005US20050129848 Patterned deposition source unit and method of depositing thin film using the same
06/16/2005US20050129843 Substrate overcoated with metal particles in liquid and stabilizers
06/16/2005US20050129839 Substrate processing apparatus and substrate processing method
06/16/2005US20050129496 Fast swapping station for wafer transport
06/16/2005US20050129489 Load lock and load lock chamber using the same
06/16/2005US20050129469 Transporting apparatus
06/16/2005US20050129372 Method and apparatus for manufacturing a transistor-outline (TO) can having a ceramic header
06/16/2005US20050129339 Static gas bearing system, stage mechanism, exposure apparatus, and device manufacturing method
06/16/2005US20050129177 Method and arrangement for producing radiation
06/16/2005US20050129078 Multicomponent barrier layers in quantum well active regions to enhance confinement and speed
06/16/2005US20050128860 Thin film magnetic memory device including memory cells having a magnetic tunnel junction
06/16/2005US20050128850 Integrated logic circuit and hierarchical design method thereof
06/16/2005US20050128843 Nonvolatile semiconductor memory
06/16/2005US20050128839 Semiconductor memory device
06/16/2005US20050128835 Semiconductor device which is low in power and high in speed and is highly integrated
06/16/2005US20050128816 Floating trap non-volatile semiconductor memory devices including high dielectric constant blocking insulating layers
06/16/2005US20050128815 Semiconductor data processing device
06/16/2005US20050128812 EEPROM device with substrate hot-electron injector for low-power programming
06/16/2005US20050128811 Nonvolatile semiconductor memory device capable of uniformly inputting/outputting data
06/16/2005US20050128806 Non-volatile semiconductor memory array structure and operations
06/16/2005US20050128804 Multi-state NROM device
06/16/2005US20050128803 Gated diode memory cells
06/16/2005US20050128802 Magnetic memory device and method for production thereof
06/16/2005US20050128800 Thin film magnetic memory device conducting read operation by a self-reference method
06/16/2005US20050128794 Method and apparatus for a high density magnetic random access memory (mram) with stackable architecture
06/16/2005US20050128787 Method of forming a memory device having a storage transistor
06/16/2005US20050128725 Device for coupling PCB sheet
06/16/2005US20050128724 Device for coupling PCB sheet
06/16/2005US20050128692 Electric circuit module and method for its assembly
06/16/2005US20050128682 Method for adjusting capacitance of an on-chip capacitor
06/16/2005US20050128681 Capacitor and its manufacturing method, and semiconductor device
06/16/2005US20050128674 Ceramic chuck
06/16/2005US20050128669 Protection device
06/16/2005US20050128663 Semiconductor device and method of manufacturing the same
06/16/2005US20050128571 Monochromator mirror for the euv-spectral range
06/16/2005US20050128540 Beam shaping element for use in a lithographic system
06/16/2005US20050128490 Apparatus for imaging metrology
06/16/2005US20050128489 Parametric optimization of optical metrology model
06/16/2005US20050128473 Method and apparatus for article inspection including speckle reduction
06/16/2005US20050128472 Method for inspecting defects and an apparatus of the same
06/16/2005US20050128471 Optical coupling for testing integrated circuits
06/16/2005US20050128463 Lithographic apparatus and device manufacturing method
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