Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
06/2005
06/09/2005US20050124171 Method of forming trench isolation in the fabrication of integrated circuitry
06/09/2005US20050124170 Strained semiconductor substrate and processes therefor
06/09/2005US20050124169 Truncated dummy plate for process furnace
06/09/2005US20050124168 Semiconductor device and method of manufacturing the same
06/09/2005US20050124167 Method for forming a cavity and an SOI in a semiconductor substrate, and a semiconductor substrate having a buried cavity and/or an SOI formed therein
06/09/2005US20050124166 In situ application of etch back for improved deposition into high-aspect-ratio features
06/09/2005US20050124165 Method for CMP removal rate compensation
06/09/2005US20050124164 Fine particle film forming apparatus and method and semiconductor device and manufacturing method for the same
06/09/2005US20050124163 Dynamic random access memory circuitry comprising insulative collars
06/09/2005US20050124162 Fabrication method for a hard mask on a semiconductor structure
06/09/2005US20050124160 Novel multi-gate formation procedure for gate oxide quality improvement
06/09/2005US20050124159 Deflectable microstructure and method of manufacturing the same through bonding of wafers
06/09/2005US20050124158 Silver under-layers for electroless cobalt alloys
06/09/2005US20050124157 Utilizing atomic layer deposition for programmable device
06/09/2005US20050124156 Semiconductor device and manufacturing process therefore
06/09/2005US20050124155 Electrode structures and method to form electrode structures that minimize electrode work function variation
06/09/2005US20050124154 Method of forming copper interconnections for semiconductor integrated circuits on a substrate
06/09/2005US20050124153 Advanced seed layery for metallic interconnects
06/09/2005US20050124152 Composite sacrificial material
06/09/2005US20050124151 Novel method to deposit carbon doped SiO2 films with improved film quality
06/09/2005US20050124150 Method for fabricating semiconductor device
06/09/2005US20050124149 Method of forming dual damascene metal interconnection employing sacrificial metal oxide layer
06/09/2005US20050124148 Method for embedding a component in a base and forming a contact
06/09/2005US20050124147 Land grid array packaged device and method of forming same
06/09/2005US20050124146 Method of fabricating strained Si SOI wafers
06/09/2005US20050124145 Mask for sequential lateral solidification and crystallization method using thereof
06/09/2005US20050124143 Defect reduction in semiconductor materials
06/09/2005US20050124142 Transposed split of ion cut materials
06/09/2005US20050124140 Pre-fabrication scribing
06/09/2005US20050124139 Process of producing multicrystalline silicon substrate and solar cell
06/09/2005US20050124138 Method for handling semiconductor layers in such a way as to thin same
06/09/2005US20050124137 Semiconductor substrate and manufacturing method therefor
06/09/2005US20050124135 Methods of forming oxide masks with submicron openings and microstructures formed thereby
06/09/2005US20050124134 STI forming method for improving STI step uniformity
06/09/2005US20050124133 Method of forming a PIP capacitor
06/09/2005US20050124132 Self-aligned MIM capacitor process for embedded DRAM
06/09/2005US20050124131 Method of forming an inductor with continuous metal deposition
06/09/2005US20050124130 Semiconductor fabrication process with asymmetrical conductive spacers
06/09/2005US20050124129 Method of fabrication of silicon-gate MIS transistor
06/09/2005US20050124128 Methods for manufacturing semiconductor device
06/09/2005US20050124127 Method for manufacturing gate structure for use in semiconductor device
06/09/2005US20050124126 Method for fabricating silicide
06/09/2005US20050124125 Non-silicon semiconductor and high-k gate dielectric metal oxide semiconductor field effect transistors
06/09/2005US20050124124 Method for fabricating a semiconductor structure
06/09/2005US20050124123 Fabrication method for semiconductor device and manufacturing apparatus for the same
06/09/2005US20050124122 Semiconductor devices and methods for fabricating the same
06/09/2005US20050124121 Anneal of high-k dielectric using NH3 and an oxidizer
06/09/2005US20050124120 Method and circuit for multiplying signals with a transistor having more than one independent gate structure
06/09/2005US20050124119 Open drain input/output structure and manufacturing method thereof in semiconductor device
06/09/2005US20050124118 Structure and method of fabricating a transistor having a trench gate
06/09/2005US20050124117 Method of fabricating flash memory device and flash memory device fabricated thereby
06/09/2005US20050124116 3D polysilicon ROM and method of fabrication thereof
06/09/2005US20050124115 Method of forming a floating gate for a stacked gate flash memory device
06/09/2005US20050124114 Semiconductor device and method for fabricating the same
06/09/2005US20050124113 Method for fabricating semiconductor device
06/09/2005US20050124112 Asymmetric-area memory cell
06/09/2005US20050124111 Method for forming a self-aligned buried strap in a vertical memory cell
06/09/2005US20050124110 Method for forming a self-aligned buried strap in a vertical memory cell
06/09/2005US20050124109 Top surface roughness reduction of high-k dielectric materials using plasma based processes
06/09/2005US20050124108 Selective polysilicon stud growth
06/09/2005US20050124107 Method of fabricating a semiconductor device with a trench isolation structure and semiconductor device
06/09/2005US20050124106 Reverse metal process for creating a metal silicide transistor gate structure
06/09/2005US20050124105 Semiconductor device and method of manufacturing the same
06/09/2005US20050124104 Methods of fabricating semiconductor device having T-shaped gate and L-shaped spacer
06/09/2005US20050124103 Method for manufacturing NAND flash device
06/09/2005US20050124102 Substrate isolation in integrated circuits
06/09/2005US20050124101 Oxide/nitride stacked in finfet spacer process
06/09/2005US20050124099 Selfaligned source/drain finfet process flow
06/09/2005US20050124098 Method of reducing noise disturbing a signal in an electronic device
06/09/2005US20050124097 Integrated circuit with two phase fuse material and method of using and making same
06/09/2005US20050124095 Sram device having high aspect ratio cell boundary
06/09/2005US20050124094 Method of producing an electronic component
06/09/2005US20050124093 Fan out type wafer level package structure and method of the same
06/09/2005US20050124091 Process for making circuit board or lead frame
06/09/2005US20050124090 Manufacturing system and apparatus for balanced product flow with application to low-stress underfilling of flip-chip electronic devices
06/09/2005US20050124089 Method of forming a seal for a semiconductor device
06/09/2005US20050124088 Method of manufacturing a thin film transistor array
06/09/2005US20050124087 Method for manufacturing electro-optical device, electro-optical device, and electronic equipment
06/09/2005US20050124086 Method for manufacturing a semiconductor device, and method for manufacturing a wafer
06/09/2005US20050124085 Process for preparation of semiconductor wafer surface
06/09/2005US20050124084 Substrate processing apparatus, control method for the apparatus, and program for implementing the method
06/09/2005US20050124083 Method for manufacturing semiconductor device
06/09/2005US20050124082 Method for manufacturing semiconductor device
06/09/2005US20050124081 Manufacturing method for a semiconductor device
06/09/2005US20050124080 Monitoring low temperature rapid thermal anneal process using implanted wafers
06/09/2005US20050124079 Modeling process for integrated circuit film resistors
06/09/2005US20050124078 Mask pattern correction method, semiconductor device manufacturing method, mask manufacturing method and mask
06/09/2005US20050123974 Methods and compositions relating to single reactive center reagents
06/09/2005US20050123859 Photosensitive composition, compound for use in the photosensitive composition, and pattern forming method using the photosensitive composition
06/09/2005US20050123858 Forming a fine hole pattern having a dimension equal to or less than a value of a resolution of an exposure tool
06/09/2005US20050123854 Alkali-soluble polysilsesquioxane with e.g. units of p-hydroxybenzylsilanetriol and phenylsilanetriol, an acid generator, and an acid decomposable ester, ether or carbonate-protected phenolic compound; wavelengths equal to or shorter than that of KrF excimer laser
06/09/2005US20050123851 Photoresist of water soluble acrylic polymers and a water soluble triazine crosslinking agent; shrinks under heat to obtain fine line patterns
06/09/2005US20050123845 Method of adjusting deviation of critical dimension of patterns
06/09/2005US20050123844 First and second alignment marks arranged one over the other; alignment based on periodicity of the Moire pattern
06/09/2005US20050123843 Analytical determination of position of an object with alignment marks; projector
06/09/2005US20050123841 an electromagnetic waveform comprising a computer program for producing a mask set including a phase shifting mask and a corresponding trim mask; semiconductors; integrated circuits
06/09/2005US20050123840 Opaque pattern consists of electrically conductive material; has a higher diffraction efficiency for projection wavelength polarised parallel to the structures than for projection light of the same wavelength polarised perpendicular; intermediate spaces filled withliquid and solid dielectrics
06/09/2005US20050123839 Photo mask capable of improving resolution by utilizing polarization of light and method of manufacturing the same
06/09/2005US20050123838 Clear field annular type phase shifting mask
06/09/2005US20050123735 Semiconductors; films; formed by crosslinking silicon containing pre-polymers at low gel temperatures via metal-ion-free onium or nucleophile catalyst
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