Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
06/2005
06/23/2005US20050134353 Semiconductor integrated circuit and manufacturing method
06/23/2005US20050134341 Duty cycle correcting circuits having a variable gain and methods of operating the same
06/23/2005US20050134309 Macrocell, integrated circuit device, and electronic instrument
06/23/2005US20050134308 Reconfigurable circuit, processor having reconfigurable circuit, method of determining functions of logic circuits in reconfigurable circuit, method of generating circuit, and circuit
06/23/2005US20050134300 Semiconductor integrated circuit and method for testing a semiconductor integrated circuit
06/23/2005US20050134256 System for processing electronic devices
06/23/2005US20050133954 Composite stamper for imprint lithography
06/23/2005US20050133938 Chip packaging compositions, packages and systems made therewith, and methods of making same
06/23/2005US20050133937 Semiconductor device, method of manufacturing thereof, circuit board and electronic apparatus
06/23/2005US20050133936 Adhesive film for manufacturing semiconductor device
06/23/2005US20050133935 Embedded redistribution interposer for footprint compatible chip package conversion
06/23/2005US20050133934 Thermal interface material bonding
06/23/2005US20050133933 Various structure/height bumps for wafer level-chip scale package
06/23/2005US20050133932 Semiconductor module with a semiconductor stack, and methods for its production
06/23/2005US20050133931 SiOC properties and its uniformity in bulk for damascene applications
06/23/2005US20050133930 Packaging substrates for integrated circuits and soldering methods
06/23/2005US20050133928 Wire loop grid array package
06/23/2005US20050133925 Forming a first conductive layer embedded in a groove formed in a dielectric film; and forming a pillar connecting an upper conductive layer to the lower and is to be self-aligned with respect to said first conductive layer without any usage of a growth guide crystallographically aligned with each other
06/23/2005US20050133924 Magnetic layer processing
06/23/2005US20050133923 Semiconductor device and method for manufacturing the same
06/23/2005US20050133921 Semiconductor device
06/23/2005US20050133920 Method and materials for self-aligned dual damascene interconnect structure
06/23/2005US20050133917 Transistor device
06/23/2005US20050133914 Semiconductor device, method of manufacturing thereof, circuit board and electronic apparatus
06/23/2005US20050133913 Stress distribution package
06/23/2005US20050133910 Metal article intended for at least partially coating with a substance and a method for producing the same
06/23/2005US20050133909 Component packaging apparatus, systems, and methods
06/23/2005US20050133908 Chip assembly with glue-strengthening holes
06/23/2005US20050133905 Method of assembling a ball grid array package with patterned stiffener layer
06/23/2005US20050133904 Method of forming metal pattern for hermetic sealing of package
06/23/2005US20050133900 Microelectronic assemblies with composite conductive elements
06/23/2005US20050133898 Printed circuit board and inkjet head
06/23/2005US20050133895 Flip-chip mounting of a semiconductor chip on a substrate for sealing by a resin for injection molding; reducing the internal pressure of the die cavity; changing the substrate clamping pressure is changed from a low pressure to a high pressure to fill the gap between chip and substrate; efficiency
06/23/2005US20050133893 Lead frame structure with aperture or groove for flip chip in a leaded molded package
06/23/2005US20050133892 Semiconductor device and method for the fabrication thereof
06/23/2005US20050133891 System and method for increasing the ball pitch of an electronic circuit package
06/23/2005US20050133890 Substrate structure capable of reducing package singular stress
06/23/2005US20050133889 Semiconductor device and method of manufacting the same, electronic module, and electronic instrument
06/23/2005US20050133887 Semiconductor component comprising areas with a high platinum concentration
06/23/2005US20050133885 Capacitor and its manufacturing method, and semiconductor device
06/23/2005US20050133883 Three-dimensional memory structure and manufacturing method thereof
06/23/2005US20050133881 Semiconductor device employing buried insulating layer and method of fabricating the same
06/23/2005US20050133878 Photosensitive semiconductor package, method for fabricating the same, and frame thereof
06/23/2005US20050133877 Chemical sensor
06/23/2005US20050133876 Reduced hydrogen sidewall spacer oxide
06/23/2005US20050133874 Method of manufactoring a semiconductor device with trench isolation between two regions having different gate insulating films
06/23/2005US20050133872 Two-layer patterned resistor
06/23/2005US20050133867 Semiconductor device and method of fabricating the same
06/23/2005US20050133866 Novel field effect transistor and method of fabrication
06/23/2005US20050133865 Member which includes porous silicon region, and method of manufacturing member which contains silicon
06/23/2005US20050133864 Semiconductor device and method of manufacturing the same
06/23/2005US20050133862 Semiconductor device and manufacturing method thereof
06/23/2005US20050133861 Vertical gate semiconductor device and method for fabricating the same
06/23/2005US20050133860 Vertical NROM NAND flash memory array
06/23/2005US20050133858 High-voltage vertical transistor with a multi-gradient drain doping profile
06/23/2005US20050133856 Vertical-type metal insulator semiconductor field effect transistor device, and production method for manufacturing such transistor device
06/23/2005US20050133854 Semiconductor device having pad structure for preventing and buffering stress of silicon nitride film
06/23/2005US20050133853 Flash memory cell and method of erasing the same
06/23/2005US20050133852 High performance embedded semiconductor memory devices with multiple dimension first-level bit-lines
06/23/2005US20050133851 Vertical NAND flash memory array
06/23/2005US20050133850 Method for forming a box shaped polygate
06/23/2005US20050133849 Semiconductor memory device having self-aligned charge trapping layer and method of manufacturing the same
06/23/2005US20050133848 Method for fabricating a lateral metal-insulator-metal capacitor and a capacitor fabricated according to the method
06/23/2005US20050133846 Deep trench capacitor with buried plate electrode and isolation collar
06/23/2005US20050133845 Integrated circuit memory cells and methods of forming
06/23/2005US20050133844 Methods of forming memory cells
06/23/2005US20050133843 Semiconductor device and method of manufacturing a semiconductor device
06/23/2005US20050133842 Semiconductor device and fabrication method of a semiconductor device
06/23/2005US20050133841 Charge-dipole coupled information storage medium
06/23/2005US20050133839 Semiconductor device
06/23/2005US20050133836 Asymmetric MOS transistor with trench-type gate
06/23/2005US20050133835 Reduced hydrogen sidewall spacer oxide
06/23/2005US20050133834 Semiconductor device and fabrication method thereof
06/23/2005US20050133833 Metal oxide semiconductor device and fabricating method thereof
06/23/2005US20050133832 Methods for selective deposition to improve selectivity
06/23/2005US20050133831 Body contact formation in partially depleted silicon on insulator device
06/23/2005US20050133830 Method for fabricating a recessed channel filed effect transistor (FET) device
06/23/2005US20050133829 High-frequency semiconductor device
06/23/2005US20050133828 Corner protection to reduce wrap around
06/23/2005US20050133827 Large-scale trimming for ultra-narrow gates
06/23/2005US20050133825 Image sensor for reduced dark current
06/23/2005US20050133824 Method for manufacturing Semiconductor device, adhesive sheet for use therein and semiconductor device
06/23/2005US20050133823 Method and apparatus for forming a wiring, wiring board, and ink set
06/23/2005US20050133821 Semiconductor device
06/23/2005US20050133820 Heterojunction bipolar transistor and method of fabricating the same
06/23/2005US20050133819 Semiconductor device using strained silicon layer and method of manufacturing the same
06/23/2005US20050133818 Gallium nitride material devices including an electrode-defining layer and methods of forming the same
06/23/2005US20050133817 Improved Cobalt Silicidation Process for Substrates with a Silicon Germanium Layer
06/23/2005US20050133812 Fabrication method of nitride semiconductors and nitride semiconductor structure fabricated thereby
06/23/2005US20050133809 Top-emitting nitride-based light emitting device and method of manufacturing the same
06/23/2005US20050133803 Flip-chip nitride light emitting device and method of manufacturing thereof
06/23/2005US20050133801 Red fluorescent material, white light emitting diode using red fluorescent material, and lighting device using white light emitting diode
06/23/2005US20050133798 Nitride semiconductor template for light emitting diode and preparation thereof
06/23/2005US20050133794 Semiconductor device
06/23/2005US20050133793 Flat panel display device and method of fabricating the same
06/23/2005US20050133792 Pixel structure and fabricating method thereof
06/23/2005US20050133791 CMOS-TFT array substrate and method for fabricating the same
06/23/2005US20050133790 Semiconductor integrated circuit, semiconductor device, and manufacturing method of the semiconductor integrated circuit
06/23/2005US20050133789 Semiconductor device having two different operation modes employing an asymmetrical buried insulating layer and method for fabricating the same
06/23/2005US20050133788 Electronic device and methods for fabricating an electronic device
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