Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
06/2005
06/14/2005US6906343 Semiconductor display device
06/14/2005US6906341 Probe needle test apparatus and method
06/14/2005US6906336 Methods for reducing blur and variation in blur in projected images produced by charged-particle-beam microlithography
06/14/2005US6906334 Curved I-core
06/14/2005US6906331 X-ray detector and method of fabricating therefore
06/14/2005US6906305 System and method for aerial image sensing
06/14/2005US6906259 High frequency module
06/14/2005US6905984 MEMS based contact conductivity electrostatic chuck
06/14/2005US6905983 Apparatus and method for manufacturing semiconductor devices, and semiconductor device
06/14/2005US6905982 Method of manufacturing a semiconductor integrated circuit device
06/14/2005US6905981 Low-k dielectric materials and processes
06/14/2005US6905980 Semiconductor device and method of manufacturing same
06/14/2005US6905978 Method of forming interlayer insulation film
06/14/2005US6905976 Structure and method of forming a notched gate field effect transistor
06/14/2005US6905975 Methods of forming patterned compositions
06/14/2005US6905974 Methods using a peroxide-generating compound to remove group VIII metal-containing residue
06/14/2005US6905973 Methods of forming semiconductor constructions
06/14/2005US6905972 Semiconductor device and method for manufacturing the same
06/14/2005US6905971 Treatment of dielectric material to enhance etch rate
06/14/2005US6905969 Plasma etch reactor and method
06/14/2005US6905968 Process for selectively etching dielectric layers
06/14/2005US6905967 Method for improving planarity of shallow trench isolation using multiple simultaneous tiling systems
06/14/2005US6905966 Method for estimating remaining film thickness distribution, method for designing patterning mask using the method for estimating remaining film thickness distribution, and method for manufacturing semiconductor devices by using patterning mask designed by using the method for estimating remaining film thickness distribution
06/14/2005US6905965 Reactive preclean prior to metallization for sub-quarter micron application
06/14/2005US6905964 Method of fabricating self-aligned metal barriers by atomic layer deposition on the copper layer
06/14/2005US6905963 Fabrication of B-doped silicon film by LPCVD method using BCI3 and SiH4 gases
06/14/2005US6905962 Method of depositing a layer
06/14/2005US6905960 Method of forming a contact in a semiconductor device
06/14/2005US6905959 Apparatus and method for depositing superior Ta (N) copper thin films for barrier and seed applications in semiconductor processing
06/14/2005US6905958 Protecting metal conductors with sacrificial organic monolayers
06/14/2005US6905957 Polishing method and polishing apparatus permitting control of polishing time at a high accuracy
06/14/2005US6905956 Multi-layer dielectric and method of forming same
06/14/2005US6905955 Methods of forming conductive connections, and methods of forming nanofeatures
06/14/2005US6905954 Method for producing a semiconductor device and corresponding semiconductor device
06/14/2005US6905953 Selective passivation of exposed silicon
06/14/2005US6905952 Recovery processing method of an electrode
06/14/2005US6905951 Method of forming a device substrate and semiconductor package including a pyramid contact
06/14/2005US6905950 Growing copper vias or lines within a patterned resist using a copper seed layer
06/14/2005US6905949 Semiconductor apparatus fabrication method forming a resist pattern, a film over the resist, and reflowing the resist
06/14/2005US6905948 Method for manufacturing semiconductor device
06/14/2005US6905947 Monatomic boron ion source and method
06/14/2005US6905946 Thin flip-chip method
06/14/2005US6905945 Microwave bonding of MEMS component
06/14/2005US6905944 Sacrificial collar method for improved deep trench processing
06/14/2005US6905943 Forming a trench to define one or more isolation regions in a semiconductor structure
06/14/2005US6905942 Semiconductor device and method of producing the same
06/14/2005US6905941 Structure and method to fabricate ultra-thin Si channel devices
06/14/2005US6905939 Process for forming silicon oxide material
06/14/2005US6905938 Method of forming interconnect structure with low dielectric constant
06/14/2005US6905936 Multi-layer capacitor and method for producing the same
06/14/2005US6905935 Method for fabricating a vertical bipolar junction transistor
06/14/2005US6905934 Semiconductor device and a method of manufacturing the same
06/14/2005US6905932 Method for constructing a metal oxide semiconductor field effect transistor
06/14/2005US6905931 Cell based integrated circuit and unit cell architecture therefor
06/14/2005US6905930 Memory device and fabrication method thereof
06/14/2005US6905928 MOS transistor apparatus and method of manufacturing same
06/14/2005US6905927 Method for forming a gate electrode in a semiconductor device including re-oxidation for restraining the thickness of the gate oxide
06/14/2005US6905926 Method of making nonvolatile transistor pairs with shared control gate
06/14/2005US6905923 Offset spacer process for forming N-type transistors
06/14/2005US6905922 Dual fully-silicided gate MOSFETs
06/14/2005US6905921 Advanced MOSFET design
06/14/2005US6905920 Method for fabrication of field-effect transistor to reduce defects at MOS interfaces formed at low temperature
06/14/2005US6905919 Method of forming a partially depleted silicon on insulator (PDSOI) transistor with a pad lock body extension
06/14/2005US6905918 SOI device with reduced drain induced barrier lowering
06/14/2005US6905917 Thin film transistor array panel for liquid crystal display and method for manufacturing the same
06/14/2005US6905916 Method for processing a surface of an SiC semiconductor layer and Schottky contact
06/14/2005US6905915 Semiconductor device and method of manufacturing the same, and electronic instrument
06/14/2005US6905914 Wafer level package and fabrication method
06/14/2005US6905912 Semiconductor device and method for fabricating the same
06/14/2005US6905910 Method of packaging an optical sensor
06/14/2005US6905909 Ultra low dielectric constant thin film
06/14/2005US6905907 Light emitting device and manufacturing method thereof
06/14/2005US6905906 Solution processed devices
06/14/2005US6905903 Display unit and method of fabricating the same
06/14/2005US6905899 Methods for forming a photoresist pattern using an anti-optical proximity effect
06/14/2005US6905898 Semiconductor substrate, method of manufacturing the semiconductor substrate, semiconductor device and pattern forming method
06/14/2005US6905897 Wafer acceptance testing method and structure of a test key used in the method
06/14/2005US6905895 Predicting process excursions based upon tool state variables
06/14/2005US6905893 Method and structure for determining a concentration profile of an impurity within a semiconductor layer
06/14/2005US6905892 Operating method for a semiconductor component
06/14/2005US6905890 Poly gate silicide inspection by back end etching and by enhanced gas etching
06/14/2005US6905889 Inductor device with patterned ground shield and ribbing
06/14/2005US6905888 Magnetic memory element having controlled nucleation site in data layer
06/14/2005US6905800 Etching a substrate in a process zone
06/14/2005US6905787 Light emitting element
06/14/2005US6905731 Wafer container and dusting prevention method thereof and method for containing wafer
06/14/2005US6905726 Component having at least two mutually adjacent insulating layers and corresponding production method
06/14/2005US6905632 Powder of pyrogenically produced silicon dioxide doped with 0.01 and 3 wt. % aluminium oxide having an average particle diameter of not more than 0.1 mu m.
06/14/2005US6905626 Notch-free etching of high aspect SOI structures using alternating deposition and etching and pulsed plasma
06/14/2005US6905625 Plasma processing method and apparatus
06/14/2005US6905624 Interferometric endpoint detection in a substrate etching process
06/14/2005US6905622 Electroless deposition method
06/14/2005US6905621 Method for preventing the etch transfer of sidelobes in contact hole patterns
06/14/2005US6905616 Method of releasing devices from a substrate
06/14/2005US6905588 Forming chip connectors; electrolytic cells
06/14/2005US6905571 Wafer polishing method and wafer polishing apparatus in semiconductor fabrication equipment
06/14/2005US6905570 Apparatus for manufacturing integrated circuit device
06/14/2005US6905560 Annealing a nickel alloy layer over a silicon to convert a portion to a monosilicide, removing remaining alloy and annealing again to reduce resistivity
06/14/2005US6905557 Multilayer structure; polishing surfaces; vertical bonding
06/14/2005US6905556 Method and apparatus for using surfactants in supercritical fluid processing of wafers
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