Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
06/2005
06/09/2005US20050123387 Apparatus for transporting and aligning disk-shaped elements
06/09/2005US20050123386 Substrate processing apparatus and substrate processing method
06/09/2005US20050123383 Substrate holding device
06/09/2005US20050123288 Gas injection head, method for manufacturing the same, semiconductor manufacturing device with the gas injection head and anti-corrosion product
06/09/2005US20050123015 Use of GaAs extended barrier layers between active regions containing nitrogen and AlGaAs confining layers
06/09/2005US20050122816 Storage device using resistance varying storage element and reference resistance value decision method for the device
06/09/2005US20050122787 Memory transistor and methods
06/09/2005US20050122784 Methods of fabricating floating trap non-volatile semiconductor memory devices including high dielectric constant blocking insulating layers
06/09/2005US20050122783 Methods of erasing a non-volatile memory device having discrete charge trap sites
06/09/2005US20050122778 Electronic memory circuit and related manufacturing method
06/09/2005US20050122775 Novolatile semiconductor memory device and manufacturing process of the same
06/09/2005US20050122773 Self-aligned, low-ressistance, efficient memory array
06/09/2005US20050122768 Nonvolatile semiconductor memory device
06/09/2005US20050122767 Memory device
06/09/2005US20050122757 Memory architecture and method of manufacture and operation thereof
06/09/2005US20050122755 Decoupling capacitors and semiconductor integrated circuit
06/09/2005US20050122748 Semiconductor device and method of manufacturing thereof
06/09/2005US20050122646 Semiconductor integrated circuit device
06/09/2005US20050122600 Lens holding technique
06/09/2005US20050122594 Objective with fluoride crystal lenses
06/09/2005US20050122589 Optical element, lithographic apparatus including such optical element and device manufacturing method, and device manufactured thereby
06/09/2005US20050122567 Manufacturing method of electro-optical apparatus substrate, manufacturing method of electro-optical apparatus, electro-optical apparatus substrate, electro-optical apparatus, and electronic instrument
06/09/2005US20050122525 Use of scanning beam for differential evaluation of adjacent regions for change in reflectivity
06/09/2005US20050122516 Overlay metrology method and apparatus using more than one grating per measurement direction
06/09/2005US20050122510 System and method for process variation monitor
06/09/2005US20050122506 Moire method and measuring system for measuring the distortion of an optical imaging system
06/09/2005US20050122505 Substrate-holding technique
06/09/2005US20050122504 Monitoring of smart pin transition timing
06/09/2005US20050122503 Lithographic apparatus and device manufacturing method
06/09/2005US20050122502 Exposure apparatus
06/09/2005US20050122501 Printing a mask with maximum possible process window through adjustment of the source distribution
06/09/2005US20050122498 Lithographic apparatus and device manufacturing method
06/09/2005US20050122493 Inert-gas purge method, exposure apparatus, device fabrication method and devices
06/09/2005US20050122492 Exposing method, exposing apparatus and device manufacturing method utilizing them
06/09/2005US20050122491 Lithographic apparatus with contamination suppression, device manufacturing method, and device manufactured thereby
06/09/2005US20050122490 Lithographic apparatus and device manufacturing method
06/09/2005US20050122485 Apparatus for use in forming colored segments of a color filter
06/09/2005US20050122452 Liquid crystal display and method of manufacturing the same
06/09/2005US20050122447 Electro-optical display device and image projection unit
06/09/2005US20050122445 Liquid crystal display device and method for fabricating the same
06/09/2005US20050122442 Liquid crystal display device and method of fabricating the same
06/09/2005US20050122300 Semiconductor device and testing method thereof
06/09/2005US20050122288 Active matrix electroluminescent display devices, and their manufacture
06/09/2005US20050122265 Apparatus and methods for constructing antennas using vias as radiating elements formed in a substrate
06/09/2005US20050122207 Thin film resistor structure and method of fabricating a thin film resistor structure
06/09/2005US20050122155 Level conversion circuit and semiconductor integrated circuit device employing the level conversion circuit
06/09/2005US20050122124 Semiconductor manufacturing device and semiconductor manufacturing method
06/09/2005US20050122040 Method of manufacturing an electroluminescent device
06/09/2005US20050122031 Light-emitting device comprising led chip and method for manufacturing this device
06/09/2005US20050122005 Piezoelectric device, liquid jetting head, ferroelectric device, electronic device and methods for manufacturing these devices
06/09/2005US20050121810 Dual port memory core cell architecture with matched bit line capacitances
06/09/2005US20050121809 Information storage apparatus and electronic device in which information storage apparatus is installed
06/09/2005US20050121805 Semiconductor device and a method of manufacturing the same
06/09/2005US20050121801 Component
06/09/2005US20050121799 Semiconductor device manufacturing method and semiconductor device manufactured thereby
06/09/2005US20050121798 Method for reducing or eliminating semiconductor device wire sweep in a multi-tier bonding device and a device produced by the method
06/09/2005US20050121797 Configuration for testing the bonding positions of conductive drops and test method for using the same
06/09/2005US20050121796 Tape circuit substrate with reduced size of base film
06/09/2005US20050121794 Semiconductor constructions
06/09/2005US20050121793 Crossed power strapped layout for full CMOS circuit design
06/09/2005US20050121792 Interconnection structure and method for forming the same
06/09/2005US20050121791 Semiconductor device including multi-layered interconnection and method of manufacturing the device
06/09/2005US20050121788 Improved stress migration resistance; Multilayer; flat substrate, dielectric, connecting wires; miniaturization
06/09/2005US20050121787 Semiconductor device and method for manufacturing the same
06/09/2005US20050121786 Substrate, interlayer interconnection structure including porous insulation film in which a volume occupation ratio of pores of diameter greater than 0.6 nanometers is less than 30%, and conductive part containing metal; parasitic capacitance, degradation prevented
06/09/2005US20050121785 Material is applied onto lower edge of chip and regions of substrate abutting chip, then first continuous metal layer is applied on back side of chip and on material and edges, second sealing metal layer is applied by solvent-free process on those regions of first metal layer that cover material
06/09/2005US20050121784 Semiconductor device package utilizing proud interconnect material
06/09/2005US20050121782 Selectively adherent substrate and method for producing the same
06/09/2005US20050121781 Semiconductor device and manufacturing method thereof
06/09/2005US20050121780 Structure of semiconductor element and its manufacturing process
06/09/2005US20050121779 Semiconductor device manufacturing method and manufacturing apparatus
06/09/2005US20050121775 Device and system for heat spreader with controlled thermal expansion
06/09/2005US20050121773 Method of manufacturing semiconductor device
06/09/2005US20050121772 Capacitor and method for manufacturing the same
06/09/2005US20050121771 Integrated chip package structure using metal substrate and method of manufacturing the same
06/09/2005US20050121769 Stacked integrated circuit packages and methods of making the packages
06/09/2005US20050121768 Silicon chip carrier with conductive through-vias and method for fabricating same
06/09/2005US20050121766 Integrated circuit and method of manufacturing an integrated circuit and package
06/09/2005US20050121765 Multi-chips bumpless assembly package and manufacturing method thereof
06/09/2005US20050121762 Sequence of substrate prebake, underfill dispense, chip placement, solder reflow and underfill cure operative stages introduces lower thermal-mechanical stress during flip chip packaging
06/09/2005US20050121761 Semiconductor device and method for fabricating the same
06/09/2005US20050121759 Semiconductor package with a chip on a support plate
06/09/2005US20050121757 Integrated circuit package overlay
06/09/2005US20050121755 Methods of fabricating integrated circuit conductive contact structures including grooves
06/09/2005US20050121753 Low-power semiconductor chip with separated power ring, method for manufacturing the same, and method for controlling the same
06/09/2005US20050121751 Carbon and halogen doped silicate glass dielectric layer and method for fabricating the same
06/09/2005US20050121750 Microelectronic device having disposable spacer
06/09/2005US20050121749 Bipolar transistor including an improved emitter structure for large emitter current free of decrease in direct current amplification factor and design method therefor
06/09/2005US20050121748 Bipolar transistor having self-aligned silicide and a self-aligned emitter contact border
06/09/2005US20050121747 Automatically passivated n-p junction and a method for making it
06/09/2005US20050121745 Method of improving the top plate electrode stress inducting voids for 1T-RAM process
06/09/2005US20050121744 High density MIM capacitor structure and fabrication process
06/09/2005US20050121741 Apparatus and method for electronic fuse with improved ESD tolerance
06/09/2005US20050121740 Gapped-plate capacitor
06/09/2005US20050121739 Method of manufacturing electro-optical device and annealing device for transparent substrate
06/09/2005US20050121738 Contact etch resistant spacers
06/09/2005US20050121737 Colors only process to reduce package yield loss
06/09/2005US20050121734 Combination catheter devices, methods, and systems
06/09/2005US20050121733 Method of forming a semiconductor device with a high dielectric constant material and an offset spacer
06/09/2005US20050121731 Formation of abrupt junctions in devices by using silicide growth dopant snowplow effect