Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
03/2014
03/06/2014US20140063976 Non-volatile semiconductor memory device adapted to store a multi-valued data in a single memory cell
03/06/2014US20140063888 Memory array plane select and methods
03/06/2014US20140063682 Electrostatic chuck
03/06/2014US20140063681 Electrostatic chuck
03/06/2014US20140063503 Etching time detection means and method for etching device
03/06/2014US20140062906 Touch screens and methods of manufacturing the same
03/06/2014US20140062641 Semiconductor transformer device and method for manufacturing the same
03/06/2014US20140062578 Semiconductor structure having an active device and method for manufacturing and manipulating the same
03/06/2014US20140062524 Jfet having width defined by trench isolation
03/06/2014US20140062087 Ball bearing supported electromagnetic microgenerator
03/06/2014US20140061955 Thermosetting resin sheet for sealing electronic component, resin-sealed type semiconductor device, and method for producing resin-sealed type semiconductor device
03/06/2014US20140061954 Semiconductor device with pre-molding chip bonding
03/06/2014US20140061952 Identification mechanism for semiconductor device die
03/06/2014US20140061951 Package on package structure and method for manufacturing same
03/06/2014US20140061950 Stackable flip chip for memory packages
03/06/2014US20140061949 Heterogeneous annealing method and device
03/06/2014US20140061948 Sensor packaging method and sensor packages
03/06/2014US20140061947 Chip stack structure and manufacturing method thereof
03/06/2014US20140061944 Semiconductor Device and Method of Forming Thick Encapsulant for Stiffness with Recesses for Stress Relief in FO-WLCSP
03/06/2014US20140061941 Semiconductor device and method of manufacturing the same
03/06/2014US20140061940 Semiconductor device and method of manufacturing the same
03/06/2014US20140061939 Semiconductor devices having bit line contact plugs and methods of manufacturing the same
03/06/2014US20140061937 Fan-Out Package Comprising Bulk Metal
03/06/2014US20140061936 Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3d integrated circuits
03/06/2014US20140061935 Method for manufacturing a layer arrangement, and a layer arrangement
03/06/2014US20140061933 Wire bond splash containment
03/06/2014US20140061932 Methods and Apparatus for Package on Package Structures
03/06/2014US20140061931 Semiconductor device including fluorine-free tungsten barrier layer and method for fabricating the same
03/06/2014US20140061930 Overlay-tolerant via mask and reactive ion etch (rie) technique
03/06/2014US20140061929 Semiconductor device and manufacturing method thereof
03/06/2014US20140061927 Chip package incorporating interfacial adhesion through conductor sputtering
03/06/2014US20140061924 Interconnect Structure and Method
03/06/2014US20140061923 Structure to increase resistance to electromigration
03/06/2014US20140061922 Semiconductor device and method for manufacturing the same
03/06/2014US20140061921 Gold bonding in semiconductor devices using porous gold
03/06/2014US20140061919 Electroplated Metallic Interconnects And Products
03/06/2014US20140061918 METHOD OF FORMING LOW RESISTIVITY TaNx/Ta DIFFUSION BARRIERS FOR BACKEND INTERCONNECTS
03/06/2014US20140061916 Semiconductor device with low resistance wiring and manufacturing method for the device
03/06/2014US20140061915 Prevention of thru-substrate via pistoning using highly doped copper alloy seed layer
03/06/2014US20140061914 Doping of copper wiring structures in back end of line processing
03/06/2014US20140061913 Aluminum Interconnection Apparatus
03/06/2014US20140061912 Patterned Graphene Structures on Silicon Carbide
03/06/2014US20140061910 Semiconductor device structures and methods for copper bond pads
03/06/2014US20140061907 Semiconductor device and method for forming the same
03/06/2014US20140061904 Semiconductor structure and method of manufacturing the same
03/06/2014US20140061902 Techniques and configurations for surface treatment of an integrated circuit substrate
03/06/2014US20140061900 Semiconductor package with improved redistribution layer design and fabricating method thereof
03/06/2014US20140061897 Bump Structures for Semiconductor Package
03/06/2014US20140061896 Die Underfill Structure And Method
03/06/2014US20140061894 Heat spreader for use within a packaged semiconductor device
03/06/2014US20140061893 Hybrid thermal interface material for ic packages with integrated heat spreader
03/06/2014US20140061891 Semiconductor chip package and manufacturing method thereof
03/06/2014US20140061888 Three dimensional (3d) fan-out packaging mechanisms
03/06/2014US20140061887 Semiconductor device and manufacturing method of semiconductor device
03/06/2014US20140061883 Leadframes, air-cavity packages, and electronic devices with offset vent holes, and methods of their manufacture
03/06/2014US20140061880 Wafer level chip scale package
03/06/2014US20140061879 Multilayer packaged semiconductor device and method of packaging
03/06/2014US20140061878 Integrated circuits and a method for manufacturing an integrated circuit
03/06/2014US20140061874 Semiconductor device and method for fabricating the same
03/06/2014US20140061873 Method for processing a wafer, and layer arrangement
03/06/2014US20140061871 Semiconductor device and method of manufacturing the same
03/06/2014US20140061868 Method of manufacturing a semiconductor device and a semiconductor device
03/06/2014US20140061867 Method for depositing one or more polycrystalline silicon layers on substrate
03/06/2014US20140061865 Semiconductor device and method of manufacturing semiconductor device
03/06/2014US20140061862 Semiconductor fin on local oxide
03/06/2014US20140061861 PLANARIZATION OF GaN BY PHOTORESIST TECHNIQUE USING AN INDUCTIVELY COUPLED PLASMA
03/06/2014US20140061860 Compound semiconductor device and method of fabricating the same
03/06/2014US20140061858 Semiconductor Device with Diagonal Conduction Path
03/06/2014US20140061855 Capacitor structure and fabricating method thereof
03/06/2014US20140061853 Plated lamination structures for integrated magnetic devices
03/06/2014US20140061851 Metal-via fuse
03/06/2014US20140061850 Semiconductor device with buried bitline and method for fabricating the same
03/06/2014US20140061849 Three-dimensional devices having reduced contact length
03/06/2014US20140061848 Schottky Isolated NMOS for Latch-Up Prevention
03/06/2014US20140061846 Diode and method of manufacturing diode
03/06/2014US20140061827 Metal Protection Layer over SiN Encapsulation for Spin-Torque MRAM Device Applications
03/06/2014US20140061823 Membrane structure for electrochemical sensor
03/06/2014US20140061820 Bulk finfet with controlled fin height and high-k liner
03/06/2014US20140061817 Hybrid Gate Process for Fabricating FinFET Device
03/06/2014US20140061816 Ion implantation device and a method of semiconductor manufacturing by the implantation of boron hydride cluster ions
03/06/2014US20140061812 Semiconductor device incorporating a multi-function layer into gate stacks
03/06/2014US20140061811 Metal Gate Structure of a Semiconductor Device
03/06/2014US20140061798 Microelectronic device with isolation trenches extending under an active area
03/06/2014US20140061794 Finfet with self-aligned punchthrough stopper
03/06/2014US20140061793 Sublithographic width finfet employing solid phase epitaxy
03/06/2014US20140061786 Double Diffused Metal Oxide Semiconductor Device and Manufacturing Method Thereof
03/06/2014US20140061780 Semiconductor device including a gate dielectric layer
03/06/2014US20140061776 Semiconductor device and method of manufacturing the same
03/06/2014US20140061775 System and method for a field-effect transistor with a raised drain structure
03/06/2014US20140061748 Non-volatile memory device and method of manufacturing the same
03/06/2014US20140061747 Memory array having connections going through control gates
03/06/2014US20140061746 Semiconductor device with buried bit line and method for fabricating the same
03/06/2014US20140061736 Semiconductor device and method of manufacturing the same
03/06/2014US20140061734 Finfet with reduced parasitic capacitance
03/06/2014US20140061733 Semiconductor Device with a Passivation Layer
03/06/2014US20140061732 Method and device to achieve self-stop and precise gate height
03/06/2014US20140061731 Tunable Schottky Diode
03/06/2014US20140061724 High Electron Mobility Transistor and Manufacturing Method Thereof
03/06/2014US20140061722 Transistors, Semiconductor Devices, and Methods of Manufacture Thereof
03/06/2014US20140061721 Mos device and method for fabricating the same
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