Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
02/2014
02/27/2014US20140057401 Compound semiconductor device with mesa structure
02/27/2014US20140057399 Using Fast Anneal to Form Uniform Ni(Pt)Si(Ge) Contacts on SiGe Layer
02/27/2014US20140057398 Memory Cells, Memory Arrays, Methods Of Forming Memory Cells, And Methods Of Forming A Shared Doped Semiconductor Region Of A Vertically Oriented Thyristor And A Vertically Oriented Access Transistor
02/27/2014US20140057397 Diode-triggered silicon controlled rectifier with an integrated diode
02/27/2014US20140057396 Method of Manufacturing a Component Comprising Cutting a Carrier
02/27/2014US20140057395 Semiconductor housing and method for the production of a semiconductor housing
02/27/2014US20140057394 Method for making a double-sided fanout semiconductor package with embedded surface mount devices, and product made
02/27/2014US20140057393 Semiconductor Device Package and Methods of Packaging Thereof
02/27/2014US20140057391 Carrier Warpage Control for Three Dimensional Integrated Circuit (3DIC) Stacking
02/27/2014US20140057372 Method for on-wafer high voltage testing of semiconductor devices
02/27/2014US20140057371 High productivity combinatorial workflow for post gate etch clean development
02/27/2014US20140057370 Dual wafer spin coating
02/27/2014US20140057369 Methods for forming interconnection line using screen printing technique
02/27/2014US20140057199 Photomask blank, photomask, and method for manufacturing photomask blank
02/27/2014US20140057100 Dicing die bond film
02/27/2014US20140056679 Wafer exchange apparatus and wafer supporting hand
02/27/2014US20140056678 Dual scara arm
02/27/2014US20140056671 Automated warehouse
02/27/2014US20140056060 Method and system for providing a magnetic tunneling junction using spin-orbit interaction based switching and memories utilizing the magnetic tunneling junction
02/27/2014US20140056053 Unipolar memory devices
02/27/2014US20140055763 Exposure apparatus, exposure method, and method for producing device
02/27/2014US20140055160 Apparatus and method for inspection of marking
02/27/2014US20140055024 Ion source devices and methods
02/27/2014US20140054803 Compound barrier layer, method for forming the same and package structure using the same
02/27/2014US20140054802 Semiconductor Device and Method of Forming RDL Using UV-Cured Conductive Ink Over Wafer Level Package
02/27/2014US20140054800 Method for manufacturing a metal pad structure of a die, a method for manufacturing a bond pad of a chip, a die arrangement and a chip arrangement
02/27/2014US20140054798 Sensor packages and method of packaging dies of differing sizes
02/27/2014US20140054797 Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof
02/27/2014US20140054796 Stacked microelectronic packages having patterened sidewall conductors and methods for the fabrication thereof
02/27/2014US20140054795 Electronic Assembly With Three Dimensional Inkjet Printed Traces
02/27/2014US20140054794 Memory process and memory structure made thereby
02/27/2014US20140054792 Package assembly and method of manufacturing the same
02/27/2014US20140054791 Through silicon via packaging structures and fabrication method
02/27/2014US20140054790 Three-dimensional integrted circuit structure and method of aluminum nitride interposer substrate
02/27/2014US20140054789 Multi-Level Vertical Plug Formation With Stop Layers of Increasing Thicknesses
02/27/2014US20140054788 Method for fabricating nanogap electrodes, nanogap electrodes array, and nanodevice with the same
02/27/2014US20140054786 Chip package and method for forming the same
02/27/2014US20140054785 Chip package structure and method for manufacturing same
02/27/2014US20140054784 Integrated Circuit Connector Access Region and Method for Making
02/27/2014US20140054783 Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof
02/27/2014US20140054782 Method for fabricating semiconductor device and semiconductor device
02/27/2014US20140054781 Copper Ball Bond Features and Structure
02/27/2014US20140054780 Method for Manufacturing an Electronic Module and an Electronic Module
02/27/2014US20140054774 Semiconductor device and method of manufacturing the same
02/27/2014US20140054764 Semiconductor package and method of manufacturing the same
02/27/2014US20140054760 Package-on-package semiconductor device
02/27/2014US20140054759 Method of manufacturing semiconductor device
02/27/2014US20140054756 Anti spacer process and semiconductor structure generated by the anti spacer process
02/27/2014US20140054755 Methods of forming semiconductor device structures, and related semiconductor device structures
02/27/2014US20140054754 Optically reactive masking
02/27/2014US20140054753 Nano-meshed structure pattern on sapphire substrate by metal self-arrangement
02/27/2014US20140054752 Semiconductor memory device and fabrication method thereof
02/27/2014US20140054748 Edge trimming method for semiconductor wafer and semiconductor wafer having trimmed edge
02/27/2014US20140054747 Bipolar transistor
02/27/2014US20140054745 Memory cell support lattice
02/27/2014US20140054743 Isolated Through Silicon Vias in RF Technologies
02/27/2014US20140054728 Semiconductor structures provided within a cavity and related design structures
02/27/2014US20140054727 Method of selectively deglazing p205
02/27/2014US20140054726 Method of producing semiconductor wafer, semiconductor wafer, method of producing semiconductor device and semiconductor device
02/27/2014US20140054724 Aligned gate-all-around structure
02/27/2014US20140054720 Semiconductor device and fabrication method therof
02/27/2014US20140054717 Integration of multiple threshold voltage devices for complementary metal oxide semiconductor using full metal gate
02/27/2014US20140054715 Semiconductor device with an inclined source/drain and associated methods
02/27/2014US20140054711 System and Method for a Vertical Tunneling Field-Effect Transistor Cell
02/27/2014US20140054710 Reduction of Proximity Effects in Field-Effect Transistors with Embedded Silicon-Germanium Source and Drain Regions
02/27/2014US20140054706 Multi-fin finfet device including epitaxial growth barrier on outside surfaces of outermost fins and related methods
02/27/2014US20140054699 Electronic device including shallow trench isolation (sti) regions with bottom oxide liner and upper nitride liner and related methods
02/27/2014US20140054698 Electronic device including shallow trench isolation (sti) regions with bottom nitride liner and upper oxide liner and related methods
02/27/2014US20140054697 Semiconductor device with field electrode and method
02/27/2014US20140054696 Novel latch-up immunity nldmos
02/27/2014US20140054694 Semiconductor Device with HCI Protection Region
02/27/2014US20140054691 Field effect transistor with gated and non-gated trenches
02/27/2014US20140054690 Semiconductor device and fabricating method thereof
02/27/2014US20140054687 Mosfet device with reduced breakdown voltage
02/27/2014US20140054682 Bidirectional field effect transistor and method
02/27/2014US20140054680 Method of forming group iii nitride semiconductor, method of fabricating semiconductor device, group iii nitride semiconductor device, method of performing thermal treatment
02/27/2014US20140054679 Doping a non-planar semiconductor device
02/27/2014US20140054678 N-type Field Effect Transistors, Arrays Comprising N-type Vertically-Oriented Transistors, Methods Of Forming An N-type Field Effect Transistor, And Methods Of Forming An Array Comprising Vertically-Oriented N-type Transistors
02/27/2014US20140054677 Arrays Comprising Vertically-Oriented Transistors, Integrated Circuitry Comprising A Conductive Line Buried In Silicon-Comprising Semiconductor Material, Methods Of Forming A Plurality Of Conductive Lines Buried In Silicon-Comprising Semiconductor Material, And Methods Of Forming An Array Comprising Vertically-Oriented Transistors
02/27/2014US20140054669 Structures and Methods for Making NAND Flash Memory
02/27/2014US20140054668 Semiconductor memory device and method of fabricating the same
02/27/2014US20140054667 Split-Gate Memory Cell With Depletion-Mode Floating Gate Channel, And Method Of Making Same
02/27/2014US20140054660 Film formation method and nonvolatile memory device
02/27/2014US20140054656 Semiconductor structure and method for manufacturing the same
02/27/2014US20140054655 Semiconductor gate structure and method of fabricating thereof
02/27/2014US20140054654 Mos transistor and process thereof
02/27/2014US20140054653 Two-step shallow trench isolation (sti) process
02/27/2014US20140054650 Method for Increasing Fin Density
02/27/2014US20140054649 Semiconductor devices and methods of forming the semiconductor devices including a retrograde well
02/27/2014US20140054648 Needle-shaped profile finfet device
02/27/2014US20140054646 Apparatus and Method for Multiple Gate Transistors
02/27/2014US20140054642 Esd protection device with improved bipolar gain using cutout in the body well
02/27/2014US20140054639 Method of fabricating vertical structure leds
02/27/2014US20140054620 Array substrate, method for manufacturing the same and display device
02/27/2014US20140054610 Semiconductor device and method for growing semiconductor crystal
02/27/2014US20140054609 Large high-quality epitaxial wafers
02/27/2014US20140054607 Group III-V Device with Strain-Relieving Layers
02/27/2014US20140054605 Composite Substrates, Light Emitting Devices and a Method of Producing Composite Substrates
02/27/2014US20140054597 Power device and packaging thereof
02/27/2014US20140054595 Composite substrate of gallium nitride and metal oxide
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