Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
06/2007
06/21/2007US20070141827 Method for forming copper line
06/21/2007US20070141826 Filling narrow and high aspect ratio openings using electroless deposition
06/21/2007US20070141825 Method of bonding flying leads
06/21/2007US20070141824 Wafer structure and bumping process
06/21/2007US20070141823 Inclusion-free uniform semi-insulating group III nitride substrates and methods for making same
06/21/2007US20070141822 Multi-step anneal method
06/21/2007US20070141821 Method of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors
06/21/2007US20070141820 Method of forming gate of semiconductor device
06/21/2007US20070141819 Method for making crystalline composition
06/21/2007US20070141818 Method of depositing materials on full face of a wafer
06/21/2007US20070141817 Non-thermal annealing of doped semiconductor material
06/21/2007US20070141816 Method of fabricating semiconductor device
06/21/2007US20070141815 Processing method, processing apparatus, crystallization method and crystallization apparatus using pulsed laser beam
06/21/2007US20070141814 Process for producing a free-standing iii-n layer, and free-standing iii-n substrate
06/21/2007US20070141813 Method of fabricating multi-freestanding GaN wafer
06/21/2007US20070141812 Low temperature doped silicon layer formation
06/21/2007US20070141811 Wafer dividing method
06/21/2007US20070141810 Wafer dividing method
06/21/2007US20070141809 Process for the singulation of integrated devices in thin semiconductor chips
06/21/2007US20070141808 Microelectromechanical system pressure sensor and method for making and using
06/21/2007US20070141807 Method for producing semiconductor device
06/21/2007US20070141806 Method for producing group III nitride based compound semiconductor device
06/21/2007US20070141805 Method for bonding plastic micro chip
06/21/2007US20070141804 Method of forming through-wafer interconnects for vertical wafer level packaging
06/21/2007US20070141803 Methods for making substrates and substrates formed therefrom
06/21/2007US20070141802 Semiconductor on glass insulator made using improved ion implantation process
06/21/2007US20070141801 Semiconductor devices, CMOS image sensors, and methods of manufacturing same
06/21/2007US20070141800 Thin-film capacitor and method for fabricating the same, electronic device and circuit board
06/21/2007US20070141799 Memory cell arrays and methods for producing memory cell arrays
06/21/2007US20070141798 Silicide layers in contacts for high-k/metal gate transistors
06/21/2007US20070141797 Semiconductor devices and methods of manufacture thereof
06/21/2007US20070141796 Nonvolatile memory device and methods of forming the same
06/21/2007US20070141795 Method of forming compressive channel layer of PMOS device using gate spacer and PMOS device having a compressed channel layer
06/21/2007US20070141794 Radiation hardened isolation structures and fabrication methods
06/21/2007US20070141793 Transistor having a protruded drain
06/21/2007US20070141792 Integrated circuit structure with improved ldmos design
06/21/2007US20070141791 Doped structure for finfet devices
06/21/2007US20070141790 Carbon nanotube energy well (CNEW) field effect transistor
06/21/2007US20070141789 Semiconductor device having a surface conducting channel and method of forming
06/21/2007US20070141788 Method for embedding non-volatile memory with logic circuitry
06/21/2007US20070141787 Method for manufacturing a vertical-gate mos transistor with countersunk trench-gate
06/21/2007US20070141786 Method of manufacturing non-volatile memory element
06/21/2007US20070141785 Method of forming floating gate array of flash memory device
06/21/2007US20070141784 Transistor structures and methods for making the same
06/21/2007US20070141783 Trench field effect transistor and method of making it
06/21/2007US20070141782 Method for manufacturing semiconductor memory
06/21/2007US20070141781 Multi-bit non-volatile memory devices and methods of fabricating the same
06/21/2007US20070141780 Methods of forming flash devices with shared word lines
06/21/2007US20070141779 Methods for Coating and Filling High Aspect Ratio Recessed Features
06/21/2007US20070141778 Metal-insulator-metal capacitor
06/21/2007US20070141777 Method of forming a contact using a sacrificial structure
06/21/2007US20070141776 Semiconductor device having capacitor and fabricating method thereof
06/21/2007US20070141775 Modulation of stress in stress film through ion implantation and its application in stress memorization technique
06/21/2007US20070141774 Method and apparatus for a deposited fill layer
06/21/2007US20070141773 Structure of semiconductor device and method of fabricating the same
06/21/2007US20070141772 Semiconductor device, its manufacturing method and electronic apparatus thereof
06/21/2007US20070141771 Integrated circuits and methods of forming a field effect transistor
06/21/2007US20070141770 Semiconductor device having an organic anti-reflective coating (arc) and method therefor
06/21/2007US20070141769 Method of manufacturing flash memory device
06/21/2007US20070141768 Method of laser annealing using linear beam having quasi-trapezoidal energy profile for increased depth of focus
06/21/2007US20070141767 Thin film transistor and method of fabricating the same
06/21/2007US20070141766 Semiconductor circuit device and design method therefor
06/21/2007US20070141765 Array substrate and liquid crystal display apparatus having the same
06/21/2007US20070141764 Method of patterning multiple-layered resist film and method of manufacturing semiconductor device
06/21/2007US20070141763 Method for manufacturing field effect transistor having channel consisting of silicon fins and silicon body and transistor structure manufactured thereby
06/21/2007US20070141762 Deletable nanotube circuit
06/21/2007US20070141761 Method for fabricating semiconductor packages, and structure and method for positioning semiconductor components
06/21/2007US20070141760 Electrical device and method of manufacturing electrical devices using film embossing techniques to embed integrated circuits into film
06/21/2007US20070141759 Method for manufacturing ic-embedded substrate
06/21/2007US20070141758 Method of manufacturing mounting substrate
06/21/2007US20070141757 Method of manufacturing flexible wiring substrate and method of manufacturing electronic component mounting structure
06/21/2007US20070141756 Leadframe and method of manufacturing the same
06/21/2007US20070141755 Ribbon bonding in an electronic package
06/21/2007US20070141754 Wire bonding system and method of use
06/21/2007US20070141753 Group III nitride based compound semiconductor device and producing method for the same
06/21/2007US20070141752 Manufacturing method of semiconductor integrated circuit device
06/21/2007US20070141751 Stackable molded packages and methods of making the same
06/21/2007US20070141750 Method of manufacturing semiconductor device
06/21/2007US20070141749 Die attachment method for LED chip and structure thereof
06/21/2007US20070141748 Extended mainframe designs for semiconductor device manufacturing equipment
06/21/2007US20070141747 Electronic device fabrication process
06/21/2007US20070141746 Methods of nanotube films and articles
06/21/2007US20070141745 Production method of a capacitor
06/21/2007US20070141744 Method of fabricating a low, dark-current germanium-on-silicon pin photo detector
06/21/2007US20070141743 Three dimensional microstructures and methods for making three dimensional microstructures
06/21/2007US20070141742 Structure and method for releasing stressy metal films
06/21/2007US20070141741 Semiconductor laminated structure and method of manufacturing nitirde semiconductor crystal substrate and nitirde semiconductor device
06/21/2007US20070141740 Method for damage avoidance in transferring an ultra-thin layer of crystalline material with high crystalline quality
06/21/2007US20070141739 Method of making light emitting device having a molded encapsulant
06/21/2007US20070141738 Method of manufacturing a collection of separate variable focus lenses
06/21/2007US20070141737 Antireflective coating
06/21/2007US20070141736 Field emission device with self-aligned gate electrode structure, and method of manufacturing same
06/21/2007US20070141735 Method of monitoring deposition temperature of a copper seed layer and method of forming a copper layer
06/21/2007US20070141734 Optical method for measuring thin film growth
06/21/2007US20070141733 Laser beam irradiation method and method of manufacturing a thin firm transistor
06/21/2007US20070141732 Structural analysis method of deep trenches
06/21/2007US20070141731 Semiconductor memory with redundant replacement for elements posing future operability concern
06/21/2007US20070141730 Substrate processing system, substrate processing method and computer-readable storage medium storing verification program
06/21/2007US20070141729 Apparatus and method for controlling plasma density profile
06/21/2007US20070141515 coating with a photoimageable ink on a carrier film, forming a photoresist layer, then exposed to developing
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