Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
09/2007
09/20/2007US20070218677 Method of Forming Self-Aligned Air-Gaps Using Self-Aligned Capping Layer over Interconnect Lines
09/20/2007US20070218676 Method for forming metal bumps
09/20/2007US20070218675 Method for manufacturing bump of wafer level package
09/20/2007US20070218674 Methods for Forming Wiring and Manufacturing Thin Film Transistor and Droplet Discharging Method
09/20/2007US20070218673 Manufacturing method of semiconductor device, reticle correcting method, and reticle pattern data correcting method
09/20/2007US20070218672 Immersion plating treatment for metal-metal interconnects
09/20/2007US20070218671 Semiconductor device having wirings formed by damascene and its manufacture method
09/20/2007US20070218670 Method of plasma enhanced atomic layer deposition of TaC and TaCN films having good adhesion to copper
09/20/2007US20070218669 Method of forming a semiconductor device and structure thereof
09/20/2007US20070218668 Controlled growth of highly uniform, oxide layers, especially ultrathin layers
09/20/2007US20070218667 Reticle containing structures for sensing electric field exposure and a method for its use
09/20/2007US20070218666 Method of manufacturing semiconductor device with regard to film thickness of gate oxide film
09/20/2007US20070218665 Cross-point memory array
09/20/2007US20070218664 Vapor-phase epitaxial growth method and vapor-phase epitaxy apparatus
09/20/2007US20070218663 Semiconductor device incorporating fluorine into gate dielectric
09/20/2007US20070218662 Antimony ion implantation for semiconductor components
09/20/2007US20070218661 Undoped gate poly integration for improved gate patterning and cobalt silicide extendibility
09/20/2007US20070218660 Diamond film formation method and film formation jig thereof
09/20/2007US20070218659 Selective silicon deposition for planarized dual surface orientation integration
09/20/2007US20070218658 Crystallization pattern and method for crystallizing amorphous silicon using the same
09/20/2007US20070218657 Deposition of crystalline layers on polymer substrates using nanoparticles and laser nanoforming
09/20/2007US20070218656 Substrate processing apparatus and substrate processing method
09/20/2007US20070218655 Method for enhancing growth of semipolar (A1,In,Ga,B)N via metalorganic chemical vapor deposition
09/20/2007US20070218654 Silicon deposition over dual surface orientation substrates to promote uniform polishing
09/20/2007US20070218653 Methods for drying semiconductor wafer surfaces using a plurality of inlets and outlets held in close proximity to the wafer surfaces
09/20/2007US20070218652 Semiconductor wafer coat layers and methods therefor
09/20/2007US20070218651 Manufacturing method of a semiconductor device
09/20/2007US20070218650 Semiconductor device, method of manufacturing thereof, and method of manufacturing base material
09/20/2007US20070218649 Semiconductor wafer thinning
09/20/2007US20070218648 Method for producing a thin IC chip using negative pressure
09/20/2007US20070218647 METHOD OF CREATING DEFECT FREE HIGH Ge CONTENT (> 25%) SiGe-ON-INSULATOR (SGOI) SUBSTRATES USING WAFER BONDING TECHNIQUES
09/20/2007US20070218646 Process for producing electric conductor
09/20/2007US20070218645 Isolation trench fill using oxide liner and nitride etch back technique with dual trench depth capability
09/20/2007US20070218644 Method of thermal processing structures formed on a substrate
09/20/2007US20070218643 Material for forming insulating film with low dielectric constant, low dielectric insulating film, method for forming low dielectric insulating film and semiconductor device
09/20/2007US20070218642 Method for producing a semiconductor component having a metallic control electrode, and semiconductor component
09/20/2007US20070218641 Fully silicided extrinsic base transistor
09/20/2007US20070218640 Semiconductor device having a gate with a thin conductive layer
09/20/2007US20070218639 Formation of a smooth polysilicon layer
09/20/2007US20070218638 Recessed gate structure and method for preparing the same
09/20/2007US20070218637 Method for forming silicon oxide film and for manufacturing capacitor and semiconductor device
09/20/2007US20070218636 Method for forming ultra thin low leakage multi gate devices using a masking layer over the semiconductor substrate
09/20/2007US20070218635 Fully-depleted castellated gate MOSFET device and method of manufacture thereof
09/20/2007US20070218634 Method of fabricating flash memory cell
09/20/2007US20070218633 Silicided nonvolatile memory and method of making same
09/20/2007US20070218632 Split gate type flash memory device and method for manufacturing same
09/20/2007US20070218631 Method for forming a non-volatile memory and a peripheral device on a semiconductor substrate
09/20/2007US20070218630 Microstructure, semiconductor device, and manufacturing method of the microstructure
09/20/2007US20070218629 Method of fabricating an integrated memory device
09/20/2007US20070218628 Electronic device including a semiconductor fin and a process for forming the electronic device
09/20/2007US20070218627 Device and a method and mask for forming a device
09/20/2007US20070218626 Method for fabricating metal-insulator-metal capacitor
09/20/2007US20070218625 Trench metal-insulator-metal (mim) capacitors integrated with middle-of-line metal contacts, and method of fabricating same
09/20/2007US20070218624 Semiconductor device and method of manufacturing the same
09/20/2007US20070218623 Method of fabricating a high dielectric constant transistor gate using a low energy plasma apparatus
09/20/2007US20070218622 Method of fabricating local interconnects on a silicon-germanium 3D CMOS
09/20/2007US20070218621 Integration of strained Ge into advanced CMOS technology
09/20/2007US20070218620 Structures and methods for making strained mosfets
09/20/2007US20070218619 Method of manufacturing nonvolatile semiconductor memory device
09/20/2007US20070218618 Interlayer dielectric under stress for an integrated circuit
09/20/2007US20070218617 Method of manufacturing semiconductor device
09/20/2007US20070218616 Semiconductor constructions, and methods of forming semiconductor constructions
09/20/2007US20070218615 Trench type MOSgated device with strained layer on trench sidewall
09/20/2007US20070218614 Semiconductor Device and Method of Manufacturing The Same, Electronic Device and Method of Manufacturing The Same, and Electronic Instrument
09/20/2007US20070218613 Fully isolated photodiode stack
09/20/2007US20070218612 Method for fabricating a recessed-gate mos transistor device
09/20/2007US20070218611 Leakage barrier for GaN based HEMT active device
09/20/2007US20070218610 Methods of making a molecular detection chip having a metal oxide silicon field effect transistor on sidewalls of a micro-fluid channel
09/20/2007US20070218609 Manufacturing method of semiconductor device
09/20/2007US20070218608 Method of manufacturing a semiconductor device
09/20/2007US20070218607 Methods of Forming Single Crystalline Layers and Methods of Manufacturing Semiconductor Devices Having Such Layers
09/20/2007US20070218606 Semiconductor device and method of manufacture thereof
09/20/2007US20070218605 Semiconductor device and method of manufacture thereof
09/20/2007US20070218604 Method of manufacturing a semiconductor device
09/20/2007US20070218603 Improved soi substrates and soi devices, and methods for forming the same
09/20/2007US20070218602 Thin film transistor and method for fabricating the same
09/20/2007US20070218601 Thin film transistor substrate for liquid crystal display device and method of manufacturing the same
09/20/2007US20070218600 Method for Making a Field Effect Transistor with Diamond-Like Carbon Channel and Resulting Transistor
09/20/2007US20070218599 Method for producing silicon wafer and silicon wafer
09/20/2007US20070218598 Method for forming ultra thin low leakage multi gate devices
09/20/2007US20070218597 Structure and method for controlling the behavior of dislocations in strained semiconductor layers
09/20/2007US20070218596 Method of manufacturing semiconductor device
09/20/2007US20070218595 Power electronics equipments
09/20/2007US20070218594 Method of forming metal wiring and method of manufacturing active matrix substrate
09/20/2007US20070218593 Method for producing semiconductor package
09/20/2007US20070218592 Green Sheet, Production Method of Green Sheet and Production Method of Electronic Device
09/20/2007US20070218591 Method for fabricating a metal protection layer on electrically connecting pad of circuit board
09/20/2007US20070218590 Plating Apparatus, Plating Method and Manufacturing Method for Semiconductor Device
09/20/2007US20070218589 Manufacturing method of multilayer wiring substrate
09/20/2007US20070218588 Integrated circuit package having stacked integrated circuits and method therefor
09/20/2007US20070218587 Soft conductive polymer processing pad and method for fabricating the same
09/20/2007US20070218586 Manufacturing method of semiconductor device
09/20/2007US20070218585 Encapsulation in a hermetic cavity of a microelectronic composite, particularly of a mems
09/20/2007US20070218584 Method for wafer-level package
09/20/2007US20070218583 Microelectronic devices and methods for manufacturing microelectronic devices
09/20/2007US20070218582 Process for making contained layers and devices made with same
09/20/2007US20070218581 Photo-masking method for fabricating TFT array substrate
09/20/2007US20070218580 Triple-junction filterless CMOS imager cell
09/20/2007US20070218579 Wide output swing CMOS imager
09/20/2007US20070218578 Real-time CMOS imager having stacked photodiodes fabricated on SOI wafer
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