Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 8 - Arrangements for selecting an address in a digital store
Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368)
02/1997
02/04/1997US5600605 Auto-activate on synchronous dynamic random access memory
02/04/1997US5600604 System for allowing a simm module with asymmetric addressing to be utilized in a computer system
02/04/1997US5600598 Memory cell and wordline driver for embedded DRAM in ASIC process
01/1997
01/30/1997WO1997003444A1 System comprising field programmable gate array and intelligent memory
01/29/1997EP0756284A2 High density two port memory cell
01/29/1997EP0756283A2 Multi-port random access memory
01/29/1997EP0756282A2 Output data holding latches for multiport memory
01/28/1997US5598375 Static random access memory dynamic address decoder with non-overlap word-line enable
01/28/1997US5598374 Pipeland address memories, and systems and methods using the same
01/28/1997US5598372 Semiconductor memory
01/23/1997DE19537888C1 Decoder gate for addressing semiconductor memory or control logic circuit
01/22/1997EP0755057A2 Semiconductor memory device
01/21/1997US5596544 Very large scale integrated planar read only memory
01/21/1997US5596543 Semiconductor memory device including circuitry for activating and deactivating a word line within a single RAS cycle
01/21/1997US5596542 Semiconductor memory device having dual word line configuration
01/21/1997US5596533 Method and apparatus for reading/writing data from/into semiconductor memory device
01/16/1997WO1997001846A1 An integrated circuit having enable control circuitry
01/14/1997US5594913 High speed memory access system for a microcontroller with directly driven low order address bits
01/14/1997US5594886 Pseudo-LRU cache memory replacement method and apparatus utilizing nodes
01/14/1997US5594765 Counter system for producing an output count
01/14/1997US5594704 Synchronous semiconductor memory device
01/14/1997US5594701 Semiconductor memory device having a plurality of blocks
01/14/1997US5594696 Improvemetns in a detection circuit with a level shifting circuit
01/08/1997EP0752759A2 Bootstrap circuit
01/07/1997US5592494 Semiconductor integrated circuit
01/07/1997US5592435 Pipelined read architecture for memory
01/07/1997US5592421 Semiconductor integrated circuit for generating an internal power source voltage with reduced potential changes
01/07/1997US5592415 Non-volatile semiconductor memory
01/07/1997US5592414 Memory cell circuit independently controlled in writing and reading
01/02/1997EP0751526A1 Bit line selection decoder, particularly for electronic memories
01/01/1997CN1139240A Data processing system, method thereof and memory cassette
12/1996
12/31/1996US5590307 Dual-port data cache memory
12/31/1996US5590089 Address transition detection (ATD) circuit
12/31/1996US5590088 Semiconductor memory device with enable signal conversion circuit operative for reducing current consumption
12/31/1996US5590087 Multi-ported data storage device with improved cell stability
12/31/1996US5590084 Semiconductor memory device having a column selector
12/31/1996US5590083 Process of writing data from a data processor to a memory device register that is separate from the array
12/31/1996US5590077 Semiconductor memory device
12/31/1996US5590071 Method and apparatus for emulating a high capacity DRAM
12/25/1996CN1138718A Method for connecting DRAM module to DRAM included in higher-order control system of full electronic exchange
12/24/1996US5588133 Register block circuit for central processing unit of microcomputer
12/24/1996US5587963 Semiconductor memory device
12/24/1996US5587960 Integrated circuit memory device with voltage boost
12/24/1996US5587959 Semiconductor memory device
12/24/1996US5587957 Circuit for sharing a memory of a microcontroller with an external device
12/24/1996US5587956 Semiconductor memory device having function of generating boosted potential
12/24/1996US5587955 Electronic token
12/24/1996US5587951 High speed, low voltage non-volatile memory
12/19/1996WO1996041345A1 Auto-activate on synchronous dynamic random access memory
12/19/1996WO1996041264A1 Static wordline redundancy memory device
12/17/1996US5586081 Synchronous address latching for memory arrays
12/17/1996US5586080 Local word line phase driver
12/17/1996US5586079 Address generating and decoding device and method with increased decoding speed
12/17/1996US5586072 Multiport memory and method
12/10/1996US5583815 Mode setting curcuit and method of a semiconductor memory device
12/10/1996US5583813 Semiconductor memory device
12/05/1996WO1996038847A1 Process for the selective programming of a non-volatile store
12/05/1996WO1996038846A1 Burst mode block write in a memory
12/05/1996WO1996038845A1 Technique for reconfiguring a high density memory
12/04/1996EP0745998A1 Circuit and method for accessing memory cells of a memory device
12/04/1996EP0745995A1 Nonvolatile, in particular flash-EEPROM, memory device
12/04/1996EP0745256A1 Method of and device for writing and reading data items in a memory system
12/03/1996US5581733 Data transfer control of a video memory having a multi-divisional random access memory and a multi-divisional serial access memory
12/03/1996US5581509 Double-row address decoding and selection circuitry for an electrically erasable and programmable non-volatile memory device with redundancy, particularly for flash EEPROM devices
12/03/1996US5581505 Ram/ROM hybrid memory architecture
12/03/1996US5581203 Semiconductor read-only VLSI memory
11/1996
11/27/1996EP0744751A2 Smart tray for audio player
11/27/1996CN1136698A Multiple end-point data storage device and operation method thereof
11/26/1996US5579279 Semiconductor memory device and method of manufacturing the same
11/26/1996US5579277 System and method for interleaving memory banks
11/26/1996US5579268 Semiconductor memory device capable of driving word lines at high speed
11/26/1996US5579264 Distributed signal drivers in arrayable devices
11/20/1996EP0743757A2 Programmable binary/interleave sequence counter
11/20/1996EP0743649A2 Serial access memory with reduced loop-line delay
11/19/1996US5577195 Semiconductor data storage device with means for protecting data upon external power supply connection and disconnection
11/19/1996US5577005 Circuit for using chip information
11/19/1996US5577003 Decoding circuit for use in semiconductor read only memory
11/19/1996US5576994 Non-volatile semiconductor memory device
11/19/1996US5576987 Semiconductor memory device
11/14/1996WO1996035992A1 Semiconductor memory having arithmetic function, and processor using the same
11/14/1996CA2220547A1 Semiconductor memory having arithmetic function, and processor using the same
11/12/1996US5574935 Superscalar processor with a multi-port reorder buffer
11/12/1996US5574880 Mechanism for performing wrap-around reads during split-wordline reads
11/12/1996US5574876 Processor system using synchronous dynamic memory
11/12/1996US5574698 Memory system
11/12/1996US5574690 Self-test device for memories, decoders, etc.
11/12/1996US5574679 Memory data protection for a ferroelectric memory
11/07/1996DE19534934A1 Decoding circuit for addressing word lines on integrated circuit e.g. IC memory
11/06/1996EP0741392A1 Using one memory to supply addresses to an associated memory during testing
11/06/1996EP0741387A2 Nonvolatile memory device with sectors of preselectable size and number
11/06/1996EP0741386A2 Decoder and decoder driver with voltage level translator
11/06/1996EP0681733A4 Memory array having a plurality of address partitions.
11/06/1996CN1135080A Self-bootstrapping device
11/05/1996US5572693 Method and apparatus for controlling extended memory chips in a random block access operation
11/05/1996US5572692 Memory configuration decoding system having automatic row base address generation mechanism for variable memory devices with row access interleaving
11/05/1996US5572482 Block architected static RAM configurable for different word widths and associated method for forming a physical layout of the static RAM
10/1996
10/31/1996WO1996034392A1 Nonvolatile memory blocking architecture
10/31/1996WO1996034391A1 Nonvolatile memory blocking architecture and redundancy
10/31/1996WO1996029637A3 Optimization circuitry and control for a synchronous memory device with programmable latency period
10/29/1996US5570320 Dual bank memory system with output multiplexing and methods using the same
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