| Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197) |
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| 01/24/2002 | US20020010827 A portable data storage device having a secure mode of operation |
| 01/24/2002 | US20020009834 Semiconductor IC device having a memory and a logic circuit implemented with a single chip |
| 01/24/2002 | US20020009014 Circuit for eliminating idle cycles in a memory device |
| 01/24/2002 | US20020009013 Interface circuit for using in high-speed semiconductor device and interfacing method |
| 01/24/2002 | US20020009009 Method for multiple match detection in content addressable memories |
| 01/24/2002 | US20020008997 High speed interface type semiconductor memory device |
| 01/24/2002 | US20020008705 Data processing apparatus having DRAM incorporated therein |
| 01/24/2002 | US20020008558 Clock generation circuit, control method of clock generation circuit and semiconductor memory device |
| 01/24/2002 | US20020008556 Delay-locked loop with binary-coupled capacitor |
| 01/24/2002 | US20020008554 Apparatus and method for tracking between data and echo clock |
| 01/24/2002 | US20020008550 Sense amplifier of semiconductor integrated circuit |
| 01/24/2002 | US20020008549 Pseudo-differential current sense amplifier with hysteresis |
| 01/24/2002 | US20020008271 Non-volatile memory system |
| 01/24/2002 | US20020008250 Memory module with hierarchical functionality |
| 01/24/2002 | DE10034082A1 Print medium incorporating various memory chips for storing different texts |
| 01/24/2002 | DE10033441A1 Circuit generating correctioon signals is integrated, dynamic semiconductor memories (DRAM) |
| 01/24/2002 | DE10032272A1 Strom-Treiberanordnung für MRAM Current driver configuration for MRAM |
| 01/24/2002 | DE10031948A1 DRAM interface has latency setting unit for adjusting latency to fixed value |
| 01/23/2002 | EP1174881A1 Integrated circuit for memory card and memory card using the circuit |
| 01/23/2002 | EP1174880A1 Data transfer system for transferring data in synchronization with system clock and synchronous semiconductor memory |
| 01/23/2002 | EP1174790A1 Method and apparatus for determining the number of empty memory locations in a FIFO memory device |
| 01/22/2002 | US6341100 Semiconductor integrated circuit having circuit for writing data to memory cell |
| 01/22/2002 | US6341099 Reducing power consumption in a data storage device |
| 01/22/2002 | US6341098 Semiconductor integrated circuit device having hierarchical power source arrangement |
| 01/22/2002 | US6341095 Apparatus for increasing pulldown rate of a bitline in a memory device during a read operation |
| 01/22/2002 | US6341089 Semiconductor memory device allowing effective detection of leak failure |
| 01/22/2002 | US6341088 Dynamic random access memory in switch MOSFETs between sense amplifiers and bit lines |
| 01/22/2002 | US6341086 Semiconductor memory circuit including a data output circuit |
| 01/22/2002 | US6340973 Memory control unit and memory control method and medium containing program for realizing the same |
| 01/22/2002 | US6340117 Apparatus and method for transferring information between a removable memory and a computer |
| 01/17/2002 | WO2002005289A1 A method and apparatus for accelerating signal equalization between a pair of signal lines |
| 01/17/2002 | WO2002005287A1 Addressing of memory matrix |
| 01/17/2002 | WO2002005284A1 Multilevel memory access method |
| 01/17/2002 | WO2002005283A1 Method and apparatus for synchronization of row and column access operations |
| 01/17/2002 | WO2002005282A1 A method and apparatus for simultaneous differential data sensing and capture in a high speed memory |
| 01/17/2002 | WO2002005281A2 A high speed dram architecture with uniform access latency |
| 01/17/2002 | WO2002005093A1 Method and circuit for accelerating redundant address matching |
| 01/17/2002 | WO2001043139A3 Method and apparatus for synchronizing dynamic random access memory exiting from a low power state |
| 01/17/2002 | US20020007435 Methods and apparatus for variable length SDRAM transfers |
| 01/17/2002 | US20020007434 Non-volatile memory capable of autonomously executing a program |
| 01/17/2002 | US20020007386 System and method for reducing timing mismatch in sample and hold circuits using an FFT and decimation |
| 01/17/2002 | US20020007277 Voice message managing method, in particular for a voice data recording/playing/editing electronic device |
| 01/17/2002 | US20020006074 Elimination of precharge operation in synchronous flash memory |
| 01/17/2002 | US20020006070 High performance memory architecture |
| 01/17/2002 | US20020005590 Digit line architecture for dynamic memory |
| 01/17/2002 | DE10134495A1 Memory component and processing method for 3-D computer objects for use in 3-D graphics applications in which object depth data are rapidly changed by comparison of new external data with internal existing data |
| 01/17/2002 | DE10103307A1 Semiconductor integrated circuit includes sub and main reset signal generator system |
| 01/17/2002 | DE10031946A1 Digital integrated circuit with built-in timing delay circuit for e.g. autorefresh DRAM, has regulatable current source in timing circuit to produce output signal with a delay with respect to reference timing |
| 01/17/2002 | DE10010886C1 Leseverstärkerteilschaltung für einen DRAM-Speicher und entsprechender DRAM-Speicher Sense amplifier part circuit for a DRAM memory and the appropriate DRAM memory |
| 01/17/2002 | CA2805048A1 A high speed dram achitecture with uniform access latency |
| 01/17/2002 | CA2803037A1 Method and apparatus for synchronization of row and column access operations |
| 01/17/2002 | CA2415218A1 Method and apparatus for synchronization of row and column access operations |
| 01/17/2002 | CA2414920A1 A high speed dram architecture with uniform access latency |
| 01/17/2002 | CA2414249A1 A method and apparatus for accelerating signal equalization between a pair of signal lines |
| 01/17/2002 | CA2414248A1 A method and apparatus for simultaneous differential data sensing and capture in a high speed memory |
| 01/16/2002 | EP1172957A1 Memory circuit, and synchronous detection circuit |
| 01/16/2002 | EP1172854A2 Semiconductor memory with random access |
| 01/16/2002 | EP1172822A1 Semiconductor device and control device for use therewith |
| 01/16/2002 | EP1172821A1 Semiconductor storage device and method for evaluating the same |
| 01/16/2002 | EP1172820A1 Programmable and electrically erasable serial readout memory by anticipation |
| 01/16/2002 | EP1172819A1 Circuit to read information from and write information into a memory cell array |
| 01/16/2002 | EP1171885A1 System and method for displaying information on the screen of a user interface device under the control of a digital audio playback device |
| 01/16/2002 | EP1025564B1 Programmable logic device memory cell circuit |
| 01/15/2002 | US6339817 Semiconductor memory including main and sub memory portions having plural memory cell groups and a bidirectional data transfer circuit |
| 01/15/2002 | US6339814 Storage and reproduction apparatus using a semiconductor memory |
| 01/15/2002 | US6339560 Semiconductor memory based on address transitions |
| 01/15/2002 | US6339558 FIFO memory device and FIFO control method |
| 01/15/2002 | US6339553 Clock generating circuit having additional delay line outside digital DLL loop and semiconductor memory device including the same |
| 01/15/2002 | US6339552 Semiconductor device |
| 01/15/2002 | US6339551 Semiconductor device with selectable pads |
| 01/15/2002 | US6339549 Semiconductor storage apparatus having main bit line and sub bit line |
| 01/15/2002 | US6339541 Architecture for high speed memory circuit having a relatively large number of internal data lines |
| 01/15/2002 | US6339345 Semiconductor device equipped with output circuit adjusting duration of high and low levels |
| 01/15/2002 | US6339343 Data I/O buffer control circuit |
| 01/10/2002 | WO2002003459A2 High-speed low-power semiconductor memory architecture |
| 01/10/2002 | WO2002003388A2 Block-level read while write method and apparatus |
| 01/10/2002 | WO2001045106A3 Mobile communication device having integrated embedded flash and sram memory |
| 01/10/2002 | WO2000067261A9 Multi-format personal digital audio player |
| 01/10/2002 | US20020004922 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same |
| 01/10/2002 | US20020004921 Method of deciding error rate and semiconductor integrated circuit device |
| 01/10/2002 | US20020004882 Semiconductor circuit and method of controlling the same |
| 01/10/2002 | US20020004881 Data transfer apparatus and data transfer method |
| 01/10/2002 | US20020004879 Burst length discriminating circuit for use in synchronous semiconductor memory and having a predetermined initialized state of power-up |
| 01/10/2002 | US20020004867 Memory device which receives an external reference voltage signal |
| 01/10/2002 | US20020004865 Protocol for communication with dynamic memory |
| 01/10/2002 | US20020004267 Sense amplifier circuit and semiconductor storage device |
| 01/10/2002 | US20020003748 Semiconductor memory having double data rate transfer technique |
| 01/10/2002 | US20020003747 Semiconductor memory device |
| 01/10/2002 | US20020003742 Line segmentation in programmable logic devices having redundancy circuitry |
| 01/10/2002 | US20020003741 Semiconductor integrated circuit device |
| 01/10/2002 | US20020003738 Semiconductor integrated circuit device |
| 01/10/2002 | US20020003737 Semiconductor device |
| 01/10/2002 | US20020003736 Semiconductor integrated circuit device |
| 01/10/2002 | US20020003735 Integrated memory |
| 01/10/2002 | US20020003734 Semiconductor memory device having sense amplifier and method for driving sense amplifier |
| 01/10/2002 | US20020003729 Semiconductor storage device and method for evaluating the same |
| 01/09/2002 | EP1170750A1 Current driver for MRAM |
| 01/09/2002 | EP1170749A2 Semiconductor device |
| 01/09/2002 | EP0960512B1 Apparatus and method for synthesizing management packets for transmission between a network switch and a host controller |
| 01/09/2002 | CN2470921Y Improved card-recording structure of assembling itself |