Patents
Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
03/2004
03/18/2004US20040051564 Fast dynamic mirror sense amplifier with separate comparison equalization and evaluation paths
03/18/2004US20040051121 Data read circuit in a semiconductor device featuring reduced chip area and increased data transfer rate
03/18/2004US20040051094 Non-volatile semiconductor memory device allowing shrinking of memory cell
03/18/2004DE10241928A1 Synchronization unit for a semiconductor memory device especially a DDR RAM or high frequency chip has temperature controlled delay device for generated and received signals
03/18/2004DE10239322A1 Integrated memory such as DRAM has evaluation unit that produces latency signal corresponding to latency value, after receiving column address and latency value
03/18/2004DE10232003B3 Schaltungsanordnung zur bitparallelen Ausgabe eines Datenwortes Circuitry for bit-parallel output of a data word
03/18/2004DE10225398B4 Halbleiterspeichervorrichtung mit Speicherzellenarrays, die zum Durchführen eines wahlfreien Zugriffs in der Lage ist A semiconductor memory device comprising memory cell arrays, which is for performing a random access in a position
03/18/2004DE10206689B4 Integrierter Speicher und Verfahren zum Betrieb eines integrierten Speichers Integrated memory and method of operating an integrated memory
03/18/2004CA2497528A1 Method of recovering overerased bits in a memory device
03/17/2004EP1398836A2 Thin film semiconductor device and manufacturing method
03/17/2004EP1398796A1 Dedicated redundancy circuits for different operations in a flash memory device and methods of operating the same
03/17/2004EP1398792A1 Semiconductor storage device
03/17/2004EP1398786A1 Pseudo bidimensional randomly accessible memory
03/17/2004EP1398785A2 Semiconductor memory
03/17/2004EP1398784A2 Memory module with hierarchical functionality
03/17/2004EP1397808A1 Steering gate and bit line segmentation in non-volatile memories
03/17/2004EP1397807A2 Asynchronous, high-bandwidth memory component using calibrated timing elements
03/17/2004EP1177558B1 Ampic dram
03/17/2004EP0976226B1 Integrated multiport switch having shared media access control circuitry
03/17/2004CN1482683A Semiconductor memory device, method for fabricating the same, and method for driving the same
03/17/2004CN1482681A 半导体集成电路装置 The semiconductor integrated circuit device
03/17/2004CN1482619A System and method for using dynamic random access memory and flash memory
03/17/2004CN1482000A Cartridge and recording apparatus
03/16/2004US6708298 Method for guaranteeing a minimum data strobe valid window and a minimum data valid window for DDR memory devices
03/16/2004US6708264 Synchronous memory device with prefetch address counter
03/16/2004US6708262 Memory device command signal generator
03/16/2004US6708261 Multi-stage data buffers having efficient data transfer characteristics and methods of operating same
03/16/2004US6708255 Variable input/output control device in synchronous semiconductor device
03/16/2004US6708249 Semiconductor integrated circuit and data processing system
03/16/2004US6708230 Relative address allocation apparatus and method for data storage card
03/16/2004US6707759 Latency control circuit and method of latency control
03/16/2004US6707758 Semiconductor memory device including clock generation circuit
03/16/2004US6707756 System and method for translation of SDRAM and DDR signals
03/16/2004US6707754 Method of constructing a very wide, very fast distributed memory
03/16/2004US6707751 Semiconductor integrated circuit device
03/16/2004US6707746 Fuse programmable I/O organization
03/16/2004US6707745 Operation control according to temperature variation in integrated circuit
03/16/2004US6707744 Apparatus for controlling refresh of memory device without external refresh command and method thereof
03/16/2004US6707743 Method and apparatus for completely hiding refresh operations in a DRAM device using multiple clock division
03/16/2004US6707742 Nonvolatile semiconductor memory device
03/16/2004US6707741 Current steering reduced bitline voltage swing, sense amplifier
03/16/2004US6707740 Semiconductor memory
03/16/2004US6707739 Two-phase pre-charge circuit and standby current erasure circuit thereof
03/16/2004US6707738 Semiconductor memory device having mesh-type structure of precharge voltage line
03/16/2004US6707736 Semiconductor memory device
03/16/2004US6707734 Method and circuit for accelerating redundant address matching
03/16/2004US6707729 Physically alternating sense amplifier activation
03/16/2004US6707728 Signal delay control circuit in a semiconductor memory device
03/16/2004US6707727 Timing signal generator for correctly transmitting a signal at high speed without waveform distortion
03/16/2004US6707726 Register without restriction of number of mounted memory devices and memory module having the same
03/16/2004US6707723 Data input circuits and methods of inputting data for a synchronous semiconductor memory device
03/16/2004US6707722 Method and apparatus for regulating predriver for output buffer
03/16/2004US6707720 Nonvolatile semiconductor storage device
03/16/2004US6707719 Nonvolatile semiconductor memory device with double data storage circuit for writing and write-verifying multi-state memory cells
03/16/2004US6707717 Current sense amplifier with dynamic pre-charge
03/16/2004US6707715 Reference generator circuit and method for nonvolatile memory devices
03/16/2004US6707705 Integrated dynamic memory device and method for operating an integrated dynamic memory
03/16/2004US6707411 Analog-to-digital converter with on-chip memory
03/16/2004US6707410 Digital pixel sensor with a dynamic comparator having reduced threshold voltage sensitivity
03/16/2004US6707321 Input receiver for controlling offset voltage using output feedback signal
03/16/2004US6707316 Circuit technique for high speed low power data transfer bus
03/11/2004WO2004021701A1 Data processing unit and method, and program
03/11/2004WO2004021573A1 Synchronous mirror delay (smd) circuit and method including a ring oscillator for timing coarse and fine delay intervals
03/11/2004WO2004021354A1 Bias sensing in dram sense amplifiers
03/11/2004WO2004021353A1 Device writing to a plurality of rows in a memory matrix simultaneously
03/11/2004WO2004021352A1 Method and apparatus for setting and compensating read latency in a high speed dram
03/11/2004US20040049663 System with wide operand architecture and method
03/11/2004US20040049629 System and method for using dynamic random access memory and flash memory
03/11/2004US20040047404 Semiconductor memory device having repeaters located at the global input/output line
03/11/2004US20040047230 Address selection circuit and semiconductor memory device with synchronous and asynchronous address signal paths
03/11/2004US20040047229 Semiconductor memory device having a hierarchical I/O structure
03/11/2004US20040047227 Integrated memory and method for setting the latency in the integrated memory
03/11/2004US20040047220 Semiconductor memory device allowing reduction of I/O terminals
03/11/2004US20040047219 Ferroelectric nonvolatile semiconductor memory
03/11/2004US20040047216 Non-volatile memory device capable of generating accurate reference current for determination
03/11/2004US20040047215 Bit line sense amplifier driving control circuits and methods for synchronous drams that selectively supply and suspend supply of operating voltages
03/11/2004US20040047211 Sense amplifiers with output buffers and memory devices incorporating same
03/11/2004US20040047209 FIFO memory devices having multi-port cache memory arrays therein that support hidden EDC latency and bus matching and methods of operating same
03/11/2004US20040047207 Reading circuit, reference circuit, and semiconductor memory device
03/11/2004US20040047202 Nonvolatile semiconductor memory
03/11/2004US20040047188 Memory with a bit line block and/or a word line block for preventing reverse engineering
03/11/2004US20040047185 Semiconductor device
03/11/2004US20040047184 Differential sense amplifier for multilevel non-volatile memory
03/11/2004US20040046595 Semiconductor memory device having a power-on reset circuit
03/11/2004US20040046213 Semiconductor memory device equipped with dummy cells
03/11/2004US20040046209 When n-channel thin film transistors(TFTs) and p-channel TFTs are formed on a polycrystalline silicon film formed on a glass substrate, a process is included in which P-dopant or N-dopant is introduced at the same time to the channel region
03/11/2004US20040046188 Static memory cell having independent data holding voltage
03/11/2004DE10338273A1 Halbleiterspeicherbauelement und Zugriffsverfahren hierfür The semiconductor memory device and access method thereof
03/11/2004DE10238279A1 Integrated semiconductor device with shift-register chain for trimming of generators, has parallel-series-converter in signal-connection with fuses storing trimming data
03/10/2004EP1396863A1 Semiconductor memory device and method for testing semiconductor memory device
03/10/2004CN1480948A Semiconductor memory able to reduce input/output terminal
03/09/2004US6704881 Method and apparatus for providing symmetrical output data for a double data rate DRAM
03/09/2004US6704828 System and method for implementing data pre-fetch having reduced data lines and/or higher data rates
03/09/2004US6704810 Method for handling persistent reservation registrations in a storage device
03/09/2004US6704734 Tuple space operations for fine grained system control
03/09/2004US6704384 Phase adjusting circuit and semiconductor memory incorporating the same
03/09/2004US6704243 Apparatus for generating memory-internal command signals from a memory operation command
03/09/2004US6704242 Semiconductor integrated circuit
03/09/2004US6704239 Non-volatile semiconductor memory device
03/09/2004US6704237 Circuits for controlling internal power supply voltages provided to memory arrays based on requested operations and methods of operating