| Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197) |
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| 04/07/2004 | EP1406265A1 Memory access collision avoidance scheme |
| 04/07/2004 | EP1405240A1 Multi input memory device reader |
| 04/07/2004 | EP1405193A2 Interface for removable storage devices |
| 04/07/2004 | CN1488147A A method for non-destructive readout and apparatus for use with the method |
| 04/07/2004 | CN1488145A MRAM bit line word line architecture |
| 04/07/2004 | CN1487528A Data output circuit and data outputting method |
| 04/07/2004 | CN1487518A Apparatus and method for providing foreign language data and sending out warning |
| 04/06/2004 | US6718449 System for data transfer between different clock domains, and for obtaining status of memory device during transfer |
| 04/06/2004 | US6718431 Apparatus and method for pipelined memory operations |
| 04/06/2004 | US6718430 Window-based flash memory storage system and management and access methods thereof |
| 04/06/2004 | US6717887 Semiconductor memory device having configuration for selecting desired delay locked loop clock |
| 04/06/2004 | US6717886 Control circuit for an S-DRAM |
| 04/06/2004 | US6717885 Switching circuit capable of improving memory write timing and method thereof |
| 04/06/2004 | US6717884 Synchronous memory device with reduced address pins |
| 04/06/2004 | US6717883 Semiconductor memory for logic-hybrid memory |
| 04/06/2004 | US6717880 Current reducing device in sense amplifier over driver scheme of semiconductor memory chips and its method |
| 04/06/2004 | US6717878 Semiconductor device |
| 04/06/2004 | US6717877 Semiconductor integration circuit device |
| 04/06/2004 | US6717875 Semiconductor memory device |
| 04/06/2004 | US6717874 Systems and methods for reducing the effect of noise while reading data in series from memory |
| 04/06/2004 | US6717873 Balanced sense amplifier control for open digit line architecture memory devices |
| 04/06/2004 | US6717872 Charging circuit and semiconductor memory device using the same |
| 04/06/2004 | US6717871 Semiconductor device with flexible redundancy system |
| 04/06/2004 | US6717869 Integrated circuit having redundant, self-organized architecture for improving yield |
| 04/06/2004 | US6717868 Semiconductor memory device and control method thereof |
| 04/06/2004 | US6717852 Nonvolatile semiconductor memory device capable of concurrently and reliably writing/erasing and reading memory cores |
| 04/06/2004 | US6717835 Semiconductor device |
| 04/06/2004 | US6717834 Dual bus memory controller |
| 04/06/2004 | US6717833 Semiconductor device |
| 04/06/2004 | US6717832 Method for data communication between a plurality of semiconductor modules and a controller module and semiconductor module configured for that purpose |
| 04/06/2004 | US6717624 Line memory in which reading of a preceding line from a first memory and writing of a current line to a second memory are performed in the same time period |
| 04/06/2004 | US6717460 Semiconductor device |
| 04/06/2004 | US6717444 Low power latch sense amplifier |
| 04/06/2004 | US6717443 Method and apparatus for mitigating the hysteresis effect in a sensing circuit |
| 04/06/2004 | US6717437 Semiconductor module |
| 04/06/2004 | US6717222 Three-dimensional memory |
| 04/06/2004 | US6717198 Miniturization while preventing hydrogen from invading capacitor dielectric film |
| 04/01/2004 | WO2004027780A1 Semiconductor memory |
| 04/01/2004 | WO2004027589A2 Clock distribution topology |
| 04/01/2004 | WO2004010435A3 A system, apparatus, and method for a flexible dram architecture |
| 04/01/2004 | WO2003081367A3 Register cell and method for writing into said register cell |
| 04/01/2004 | US20040064661 Method of operating a memory at high speed using a cycle ready status output signal |
| 04/01/2004 | US20040064657 Memory structure including information storage elements and associated validity storage elements |
| 04/01/2004 | US20040064636 Storage device, storage device controlling method, and program |
| 04/01/2004 | US20040064624 Playback apparatus and access method of playback apparatus |
| 04/01/2004 | US20040064606 Memory system allowing fast operation of processor while using flash memory incapable of random access |
| 04/01/2004 | US20040063283 Eeprom with split gate source side injection |
| 04/01/2004 | US20040063271 Synchronous semiconductor device and method of preventing coupling between data buses |
| 04/01/2004 | US20040062137 Method and apparatus for DLL lock latency detection |
| 04/01/2004 | US20040062136 Indication of the system operation frequency to a dram during power-up |
| 04/01/2004 | US20040062129 Method and apparatus for enhancing the efficiency of dynamic RAM |
| 04/01/2004 | US20040062124 Memory cell configuration for a DRAM memory with a contact bit terminal for two trench capacitors of different rows |
| 04/01/2004 | US20040062122 Method of accessing matrix data with address translation circuit that enables quick serial access in row or column directions |
| 04/01/2004 | US20040062121 Semiconductor memory device having duty cycle correction circuit and interpolation circuit interpolating clock signal in the semiconductor memory device |
| 04/01/2004 | US20040062117 Adjustable current mode differential amplifier for multiple bias point sensing of MRAM having diode isolation |
| 04/01/2004 | US20040062116 Semiconductor memory device and current mirror circuit |
| 04/01/2004 | US20040062106 System and method for retrieving information from a database |
| 04/01/2004 | US20040062101 Semiconductor memory device and method for arranging memory cells |
| 04/01/2004 | US20040062091 Cycle ready circuit for self-clocking memory device |
| 04/01/2004 | US20040062090 Synchronous semiconductor memory device of fast random cycle system and test method thereof |
| 04/01/2004 | US20040062088 Semiconductor memory device based on dummy-cell method |
| 04/01/2004 | US20040062087 Memory device having high bus efficiency of network, operating method of the same, and memory system including the same |
| 04/01/2004 | US20040062073 Bitline equalization system for a DRAM integrated circuit |
| 04/01/2004 | US20040062069 Digit line architecture for dynamic memory |
| 04/01/2004 | US20040061156 Magnetic random access memory having transistor of vertical structure with writing line formed on an upper portion of the magnetic tunnel junction cell |
| 04/01/2004 | DE10344020A1 Halbleiterspeicherbaustein mit Bitleitungsspannungsausgleich Semiconductor memory device having Bitleitungsspannungsausgleich |
| 04/01/2004 | DE10260823A1 Integrated random-access memory circuit has data terminals for different regions of each memory bank coupled to common databus via single data line with anti-parallel write-in and read-out amplifiers |
| 04/01/2004 | DE10244401A1 DDR component esp. DDR-DRAM for clocked coordination and commutation of data, comprises first and second clock-pulse relaying devices for differential and single-ended clock signals |
| 04/01/2004 | DE10244400A1 Circuit arrangement with clock-signal detection device e.g. for memory devices such as CMOS type, includes clock signal ascertainment device for detecting whether clock signal is present at terminal |
| 03/31/2004 | EP1402641A2 Method and apparatus for a clock circuit |
| 03/31/2004 | EP1402532A2 Sense amplifier with improved latching |
| 03/31/2004 | EP1402531A2 Dram with bit line precharging, inverted data writing, retained data output and reduced power consumption |
| 03/31/2004 | EP1402340A2 First-in, first-out memory system and method thereof |
| 03/31/2004 | EP1402329A2 Low latency multi-level communication interface |
| 03/31/2004 | CN1486478A Display device |
| 03/31/2004 | CN1485858A Device and method for selecting power down exit |
| 03/31/2004 | CN1485855A 定时调整电路和半导体存储装置 Timing adjusting circuit and a semiconductor memory device |
| 03/31/2004 | CN1485852A 半导体存储器 Semiconductor memory |
| 03/31/2004 | CN1144229C Semiconductor integrated circuit device |
| 03/31/2004 | CN1144228C Semiconductor integrated circuit device |
| 03/31/2004 | CN1144227C Semiconductor memory of layer position line structure with improved position line pre-charging system |
| 03/31/2004 | CN1144226C Readout amplifier circuit |
| 03/31/2004 | CN1144159C Storage appts. and writing and/or reading methods for use in hierarchical coding |
| 03/31/2004 | CN1144129C Semiconductor circuit |
| 03/30/2004 | US6715115 Semiconductor integrated circuit device capable of outputting leading data of a series of multiple burst-readout data without delay |
| 03/30/2004 | US6715041 Non-volatile memory device with multiple ports |
| 03/30/2004 | US6715028 Data selecting memory device and selected data transfer device |
| 03/30/2004 | US6715020 Synchronous integrated circuit device |
| 03/30/2004 | US6714477 Semiconductor integrated circuit device with memory blocks and a write buffer capable of storing write data from an external interface |
| 03/30/2004 | US6714475 Fast accessing of a memory device using decoded address during setup time |
| 03/30/2004 | US6714474 Method of checking the state of a capacitor fuse in which the voltage applied to the capacitor fuse is the same level as voltage applied to memory cells |
| 03/30/2004 | US6714473 Method and architecture for refreshing a 1T memory proportional to temperature |
| 03/30/2004 | US6714472 Dummy wordline for controlling the timing of the firing of sense amplifiers in a memory device in relation to the firing of wordlines in the memory device |
| 03/30/2004 | US6714471 Semiconductor memory device having preamplifier with improved data propagation speed |
| 03/30/2004 | US6714470 High-speed read-write circuitry for semi-conductor memory devices |
| 03/30/2004 | US6714469 On-chip compression of charge distribution data |
| 03/30/2004 | US6714468 Circuit and method for testing a memory device |
| 03/30/2004 | US6714467 Block redundancy implementation in heirarchical RAM's |
| 03/30/2004 | US6714465 Memory device and process for improving the state of a termination |
| 03/30/2004 | US6714464 System and method for a self-calibrating sense-amplifier strobe |