Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 7 - Arrangements for writing information into, or reading information out from, a digital store
Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
11/2003
11/04/2003US6643189 Memory device
11/04/2003US6643182 Semiconductor device
11/04/2003US6643179 Method and circuit for dynamic reading of a memory cell, in particular a multi-level nonvolatile memory cell
11/04/2003US6643178 System for source side sensing
11/04/2003US6643172 Bit line decoding scheme and circuit for dual bit memory with a dual bit selection
11/04/2003US6643164 Method and circuit for determining sense amplifier sensitivity
11/04/2003US6643163 Semiconductor device
11/04/2003US6643160 Data bus architecture for integrated circuit devices having embedded dynamic random access memory (DRAM) with a large aspect ratio providing reduced capacitance and power requirements
11/04/2003US6642761 Interface circuit of various clock period between a fast slope signal and a very slow slope, voltage controlled delay cell
11/04/2003US6642757 Semiconductor memory device having a power-on reset circuit
11/04/2003US6642749 Latching sense amplifier with tri-state output
11/04/2003US6642740 Programmable termination circuit and method
10/2003
10/30/2003WO2003090232A1 Non-volatile memory and method for reading out therefrom
10/30/2003WO2003090231A2 Method of performing access to a single-port memory device, memory access device, integrated circuit device and method of use of an integrated circuit device
10/30/2003WO2003090230A2 Variable delay compensation for data-dependent mismatch in characteristic of opposing devices of a sense amplifier
10/30/2003WO2003028033A3 Segmented metal bitlines
10/30/2003WO2002095761A3 Apparatus and method for memory storage cell leakage cancellation scheme
10/30/2003US20030204763 Memory controller and method of aligning write data to a memory device
10/30/2003US20030204688 Method and apparatus for selectively transmitting command signal and address signal
10/30/2003US20030204674 Synchronous dram with selectable internal prefetch size
10/30/2003US20030204667 Destructive-read random access memory system buffered with destructive-read memory cache
10/30/2003US20030203585 Shared bit line cross-point memory array incorporating P/N junctions and method
10/30/2003US20030202412 Semiconductor memory device with internal data reading timing set precisely
10/30/2003US20030202411 System for control of pre-charge levels in a memory device
10/30/2003US20030202410 Semiconductor device with self refresh test mode
10/30/2003US20030202409 Semiconductor memory device having test mode and memory system using the same
10/30/2003US20030202406 Compact analog-multiplexed global sense amplifier for RAMs
10/30/2003US20030202405 High performance semiconductor memory devices
10/30/2003US20030202404 Memory device with row and column decoder circuits arranged in a checkboard pattern under a plurality of memory arrays
10/30/2003US20030202403 Reducing the effects of noise in non-volatile memories through multiple reads
10/30/2003US20030202399 Self-timed activation logic for memory
10/30/2003US20030202395 Circuit for removing noise form power line and semiconductor memory device having the circuit
10/30/2003US20030202393 Semiconductor memory device and control method thereof
10/30/2003US20030202391 Dummy cell structure for 1T1C FeRAM cell array
10/30/2003US20030202388 Integrated circuit having redundant, self-organized architecture for improving yield
10/30/2003US20030202385 Method for controlling column decoder enable timing in synchronous semiconductor device and apparatus thereof
10/30/2003US20030202383 Memory system
10/30/2003US20030202374 Semiconductor memory device
10/30/2003US20030201817 Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions
10/30/2003US20030201803 Low-power driver with energy recovery
10/30/2003US20030201793 Line segmentation in programmable logic devices having redundancy circuitry
10/29/2003EP1356363A2 System and method for managing information objects
10/29/2003CN1452315A IC device for providing constant time delay independent of temp.
10/29/2003CN1452178A 半导体存储器件 A semiconductor memory device
10/29/2003CN1126109C Memory and semiconductor device
10/29/2003CN1126108C Memory device with data output buffer and control method thereof
10/29/2003CN1126105C Write control drive circuit
10/29/2003CN1126104C Low power memory including selective precharge circuit
10/28/2003US6640309 Computer system providing low skew clock signals to a synchronous memory unit
10/28/2003US6640295 Semiconductor circuit with address translation circuit that enables quick serial access in row or column directions
10/28/2003US6640266 Method and device for performing write operations to synchronous burst memory
10/28/2003US6639869 Clock-synchronous semiconductor memory device
10/28/2003US6639868 SDRAM having data latch circuit for outputting input data in synchronization with a plurality of control signals
10/28/2003US6639865 Memory device, method of accessing the memory device, and reed-solomon decoder including the memory device
10/28/2003US6639852 Sensing apparatus for a ROM memory device
10/28/2003US6639849 Nonvolatile semiconductor memory device programming second dynamic reference cell according to threshold value of first dynamic reference cell
10/28/2003US6639847 Elimination of address-sensitivity by synchronous reference for sense amplifier
10/28/2003US6639846 Method and circuit configuration for a memory for reducing parasitic coupling capacitances
10/28/2003US6639845 Data holding circuit having backup function
10/28/2003US6639833 Method and circuit for dynamic reading of a memory cell at low supply voltage and with low output dynamics
10/28/2003US6639828 Static memory cell having independent data holding voltage
10/28/2003US6639825 Data memory
10/28/2003US6639822 Dynamic ram-and semiconductor device
10/23/2003WO2003088459A2 Low-power driver with energy recovery
10/23/2003WO2003088261A1 System and method for generating a reference voltage based on averaging the voltages of two complementary programmed dual bit reference cells
10/23/2003WO2003088254A1 Storage device using resistance varying storage element and reference resistance value decision method for the device
10/23/2003WO2003088252A1 Single-ended current sense amplifier
10/23/2003WO2003001673A3 Determining phase relationships using digital phase values
10/23/2003WO2002073619A3 System latency levelization for read data
10/23/2003US20030200452 Playback apparatus and playback method
10/23/2003US20030200417 Process for controlling reading data from a DRAM array
10/23/2003US20030200416 Synchronous dram system with control data
10/23/2003US20030200415 Synchronous data transfer system
10/23/2003US20030200381 Synchronous DRAM with control data buffer
10/23/2003US20030199262 Multi-clock domain data input-processing device having clock-reciving locked loop and clock signal input method thereof
10/23/2003US20030199123 Clock distribution networks and conductive lines in semiconductor integrated
10/23/2003US20030198121 Semiconductor memory device
10/23/2003US20030198119 Simultaneous function dynamic random access memory device technique
10/23/2003US20030198116 Semiconductor memory device equipped with control circuit for controlling memory cell array in non-normal operation mode
10/23/2003US20030198114 Proportional to temperature voltage generator
10/23/2003US20030198113 Memory storage device with heating element
10/23/2003US20030198112 Variable delay compensation for data-dependent mismatch in characteristic of opposing devices of a sense amplifier
10/23/2003US20030198110 Semiconductor integrated circuit device
10/23/2003US20030198108 Drive circuit and control method
10/23/2003US20030198107 Method of checking the state of a capacitor fuse in which the voltage applied to the capacitor fuse is the same level as voltage applied to memory cells
10/23/2003US20030198105 Clock recovery circuit and data receiving circuit
10/23/2003US20030198102 Non-volatile semiconductor memory device
10/23/2003US20030198097 Semiconductor memory device having preamplifier with improved data propagation speed
10/23/2003US20030198093 Methods of fabricating an mram device using chemical mechanical polishing
10/23/2003US20030198084 Nonvolatile semiconductor memory
10/23/2003US20030198083 Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics
10/23/2003US20030198078 Sensing method and apparatus for resistance memory device
10/23/2003US20030198074 Mask ROM
10/23/2003US20030198072 High speed data bus
10/23/2003US20030197239 Clock distribution networks and conductive lines in semiconductor integrated circuits
10/23/2003US20030197201 Semiconductor device
10/23/2003CA2481336A1 Single-ended current sense amplifier
10/22/2003EP1355444A2 Clock recovery circuit and data receiving circuit
10/22/2003EP1118937B1 Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics
10/22/2003CN1450564A Balance symmetric type read-out amplifier circuit for nonvolatile memory
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