Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
11/2001
11/15/2001US20010042220 Clock control circuit for rambus dram
11/15/2001US20010042216 Memory interface systems that couple a memory to a memory controller and are responsive to a terminal voltage that is independent of supply voltages for the memory and the memory controller
11/15/2001US20010042163 Ram controller interface device for ram compatibility
11/15/2001US20010042161 Semiconductor redundant memory provided in common
11/15/2001US20010041373 Thin film ferroelectric capacitors having improved memory retention through the use of essentially smooth bottom electrode structures
11/15/2001US20010040835 Semiconductor integrated circuit device
11/15/2001US20010040834 Semiconductor integrated circuit device having a hierarchical power source configuration
11/15/2001US20010040833 Method and apparatus for self timing refresh
11/15/2001US20010040832 Method for checking a semiconductor memory device
11/15/2001US20010040831 Dual floating gate programmable read only memory cell structure and method for its fabrication and operation
11/15/2001US20010040829 Semiconductor integrated circuit device capable of performing operational test for contained memory core at operating frequency higher than that of memory tester
11/15/2001US20010040828 Multidimensional addressing architecture for electronic devices
11/15/2001US20010040827 Semiconductor memory device
11/15/2001US20010040826 Method and apparatus for programming multi-state cells in a memory device
11/15/2001US20010040825 Analog voltage supply circuit for a non-volatile memory
11/15/2001US20010040824 Electrically alterable non-volatile memory with n-bits per cell
11/15/2001US20010040821 Nonvolatile semiconductor memory device
11/15/2001US20010040820 Memory using insulator traps
11/15/2001US20010040819 Magnetoresistive device and magnetic memory using the same
11/15/2001US20010040818 Dynamic flop with power down mode
11/15/2001US20010040817 SRAM having a reduced chip area
11/15/2001US20010040816 Reduced leakage DRAM storage unit
11/15/2001US20010040815 Ferroelectric memory device and method for operating ferroelectric memory device
11/15/2001US20010040814 Semiconductor memory device
11/15/2001US20010040778 Limiting magnetoresistive electrical interaction to a preferred portion of a magnetic region in magnetic devices
11/15/2001US20010040604 Ink jet printhead that incorporates through-chip ink ejection nozzle arrangements
11/15/2001US20010040474 Clock control method and circuit
11/15/2001US20010040471 I/O interface circuit, semiconductor chip and semiconductor system
11/15/2001US20010040469 Logic circuit with single charge pulling out transistor and semiconductor integrated circuit using the same
11/15/2001DE10019697A1 Spin polarization of charge carrier systems in solid bodies comprises applying a inhomogeneous magnetic field produced by a structure in the region of a solid body or on the surface of a solid body
11/14/2001EP1154487A1 Semiconductor memory and method of driving semiconductor memory
11/14/2001EP1154439A1 Programming flash memory analog storage using coarse-and-fine sequence
11/14/2001EP1154436A2 Semiconductor memory device
11/14/2001EP1154435A2 Write circuitry for a synchronous ram
11/14/2001EP1153434A1 Microelectronic device for storing information and method thereof
11/14/2001EP1153394A1 Method for operating a memory cell array with self-amplifying dynamic memory cells
11/14/2001EP1078371B1 Circuit with a sensor and non-volatile memory
11/14/2001EP0731972B1 A capacitorless dram device on silicon-on-insulator substrate
11/14/2001CN1322379A Nonvolatile memory
11/14/2001CN1322360A Integrated memory with differential read amplifier
11/14/2001CN1321986A Integrated memory having plate conducting line segment
11/14/2001CN1321985A Magnetic random access memory
11/13/2001US6317852 Method to test auto-refresh and self refresh circuitry
11/13/2001US6317657 Method to battery back up SDRAM data on power failure
11/13/2001US6317383 Detection circuit for detecting timing of two node signals
11/13/2001US6317380 Circuit for driving nonvolatile ferroelectric memory
11/13/2001US6317377 Semiconductor memory device
11/13/2001US6317376 Reference signal generation for magnetic random access memory devices
11/13/2001US6317375 Method and apparatus for reading memory cells of a resistive cross point array
11/13/2001US6317373 Semiconductor memory device having a test mode and semiconductor testing method utilizing the same
11/13/2001US6317372 Semiconductor memory device equipped with serial/parallel conversion circuitry for testing memory cells
11/13/2001US6317371 Storage device with an error correction unit and an improved arrangement for accessing and transferring blocks of data stored in a non-volatile semiconductor memory
11/13/2001US6317369 Semiconductor device allowing higher speed data transmission to and from external unit
11/13/2001US6317366 Dynamic random access memory
11/13/2001US6317365 Semiconductor memory cell
11/13/2001US6317364 Multi-state memory
11/13/2001US6317363 Multi-state memory
11/13/2001US6317359 Non-volatile magnetic circuit
11/13/2001US6317357 Vertical bipolar read access for low voltage memory cell
11/13/2001US6317356 Configuration for self-referencing ferroelectric memory cells
11/13/2001US6317355 Nonvolatile ferroelectric memory device with column redundancy circuit and method for relieving failed address thereof
11/13/2001US6317354 Non-volatile random access ferromagnetic memory with single collector sensor
11/13/2001US6317351 Associative cache memory capable of reconfiguring a K-way and N-set cache memory into a M-unit, K-way and N/M-set cache memory
11/13/2001US6317192 Utilization of image tiling effects in photographs
11/13/2001US6317007 Delayed start oscillator circuit
11/13/2001US6316985 Substrate voltage generating circuit provided with a transistor having a thin gate oxide film and a semiconductor integrated circuit device provided with the same
11/13/2001US6316968 Sense amplifier circuit
11/13/2001US6316963 Cycle selection circuit and semiconductor memory storage using the same
11/13/2001US6316921 Power supply control system
11/13/2001US6316843 Shared charge pump voltage ramp
11/13/2001US6316812 Static semiconductor memory device with expanded operating voltage range
11/08/2001WO2001084643A2 Method for producing magnetic tunnel contacts, and such a magnetic tunnel contact
11/08/2001WO2001084634A1 Information processing structure
11/08/2001WO2001084561A2 Tunable devices incorporating bicu3ti3feo¿12?
11/08/2001WO2001084554A1 Reduction of data dependent power supply noise when sensing the state of a memory cell
11/08/2001WO2001084552A2 Programming of nonvolatile memory cells
11/08/2001WO2001054279B1 A register having a ferromagnetic memory cells
11/08/2001WO2001009900A8 High speed latch and flip-flop
11/08/2001US20010039605 Virtual channel memory access controlling circuit
11/08/2001US20010039602 Semiconductor memory device and method of controlling the same
11/08/2001US20010039124 Memory device and manufacturing method therefor
11/08/2001US20010038569 Semiconductor integrated circuit device
11/08/2001US20010038567 Semiconductor memory device for fast access
11/08/2001US20010038566 Memory component with short access time
11/08/2001US20010038565 Memory circuit with automatic precharge function, and integrated circuit device with automatic internal command function
11/08/2001US20010038563 Reduction of data dependent power supply noise when sensing the state of a memory cell
11/08/2001US20010038562 Integrated memory having a differential sense amplifier
11/08/2001US20010038561 Integrated semiconductor memory having memory cells with a ferroelectric memory property
11/08/2001US20010038560 Semiconductor memory device for reducing parasitic resistance of the I/O lines
11/08/2001US20010038557 Circuit configuration for generating a reference voltage for reading a ferroelectric memory
11/08/2001US20010038553 Mixed mode multi-level memory
11/08/2001US20010038552 Semiconductor memory with switches for reducing leakage current
11/08/2001US20010038551 Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device.
11/08/2001US20010038550 Quad state memory design methods, circuits, and systems
11/08/2001US20010038548 Write circuit for large MRAM arrays
11/08/2001US20010038304 Fault tolerant storage cell
11/08/2001US20010038135 Memory using insulator traps
11/08/2001US20010038133 Full CMOS SRAM cell
11/08/2001US20010038117 Ferroelectric transistor, use thereof in a memory cell confuguration and method of producing the ferroelectric transistor
11/08/2001US20010038110 Method of making high density semiconductor memory
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