Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
12/2001
12/06/2001US20010048621 Method for testing a multiplicity of word lines of a semiconductor memory configuration
12/06/2001US20010048620 Layout of a sense amplifier with accelerated signal evaluation
12/06/2001US20010048617 Semiconductor integrated circuit
12/06/2001US20010048616 Semiconductor device including multi-chip
12/06/2001US20010048614 Programming and erasing methods for a reference cell of an nrom array
12/06/2001US20010048608 Magnetic random access memory circuit
12/06/2001US20010048509 Ink distribution assembly for an ink jet printhead
12/06/2001US20010048338 Boosting method and apparatus
12/06/2001US20010048331 Semiconductor integrated circuit and delayed clock signal generation method
12/06/2001US20010048328 Semiconductor integrated circuit
12/06/2001US20010048319 Semiconductor integrated circuit device
12/06/2001US20010048128 Semiconductor element and semiconductor memory device using the same
12/05/2001EP1160795A1 Reference cells matrix structure for reading data in a nonvolatile memory device
12/05/2001EP1160794A1 Circuit structure for programming data in reference cells of a multibit non-volatile memory device
12/05/2001EP1159743A1 Programmable microelectronic devices and methods of forming and programming same
12/05/2001CN1325549A Ferroelectric transistor, its use in storage cell system and its method of production
12/05/2001CN1325547A Semiconductor circuit
12/04/2001US6327664 Power management on a memory card having a signal processing element
12/04/2001US6327642 Parallel access virtual channel memory system
12/04/2001US6327558 Apparatus for simulating electrical characteristics of a circuit including a ferroelectric device and a method for simulating electrical characteristics of a circuit including a ferroelectric device
12/04/2001US6327217 Variable latency buffer circuits, latency determination circuits and methods of operation thereof
12/04/2001US6327216 Full page increment/decrement burst for DDR SDRAM/SGRAM
12/04/2001US6327215 Local bit switch decode circuit and method
12/04/2001US6327213 Semiconductor integrated circuit device having a hierarchical power source configuration
12/04/2001US6327210 Semiconductor memory device
12/04/2001US6327209 Multi stage refresh control of a memory device
12/04/2001US6327208 Semiconductor memory device having self refresh mode
12/04/2001US6327206 Semiconductor memory device including serial/parallel conversion circuit
12/04/2001US6327204 Method of storing information in a memory cell
12/04/2001US6327203 Memory device having minimized power consumption and data read and write method of the same
12/04/2001US6327200 Circuit and method for testing a memory device
12/04/2001US6327198 Semiconductor memory device having a test mode setting circuit
12/04/2001US6327195 Boosted-voltage drive circuit operable with high reliability and semiconductor memory device employing the same
12/04/2001US6327192 Method and circuit for providing a memory device having hidden row access and row precharge times
12/04/2001US6327191 Address signal generator in a semiconductor memory
12/04/2001US6327190 Complementary differential input buffer for a semiconductor memory device
12/04/2001US6327189 Electrically alterable non-volatile memory with n-bits per cell
12/04/2001US6327188 Synchronous random access memory
12/04/2001US6327178 Programmable circuit and its method of operation
12/04/2001US6327176 Single event upset (SEU) hardened latch circuit
12/04/2001US6327175 Method and apparatus for controlling a memory array with a programmable register
12/04/2001US6327173 Method for writing and reading a ferroelectric memory
12/04/2001US6327172 Ferroelectric non-volatile memory device
12/04/2001US6327170 Reducing impact of coupling noise in multi-level bitline architecture
12/04/2001US6326837 Data processing circuit having a waiting mode
12/04/2001US6326834 Pump circuit boosting a supply voltage
12/04/2001US6326833 Highly effective charge pump employing NMOS transistors
12/04/2001US6326815 Sense amplifier of semiconductor integrated circuit
12/04/2001US6326809 Apparatus for and method of eliminating single event upsets in combinational logic
12/04/2001US6326695 Twisted bit line structures and method for making same
12/04/2001US6326217 High-efficiency miniature magnetic integrated circuit structures
11/2001
11/29/2001WO2001091296A2 Block ram having multiple configurable write modes for use in a field programmable gate array
11/29/2001WO2001091185A2 Ultra-late programming rom and method of manufacture
11/29/2001WO2001091128A2 Semiconductor memory and controlling method thereof
11/29/2001US20010047464 Synchronous semiconductor memory device having a burst mode for improving efficiency of using the data bus
11/29/2001US20010047449 Semiconductor memory device and computer having a synchronization signal indicating that the memory data output is valid
11/29/2001US20010046272 DLL circuit
11/29/2001US20010046176 Semiconductor memory device having prefetch operation mode and data transfer method for reducing the number of main data lines
11/29/2001US20010046174 Method and apparatus for reducing bleed currents within a DRAM array having row-to-column shorts
11/29/2001US20010046173 Semiconductor memory device
11/29/2001US20010046167 Semiconductor device including multi-chip
11/29/2001US20010046164 Dual floating gate programmable read only memory cell structure and method for its fabrication and operation
11/29/2001US20010046162 Dynamic memory word line driver scheme
11/29/2001US20010046155 Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device
11/29/2001US20010046154 Circuits and methods for a memory cell wirh a trench plate trench capacitor and a vertical bipolar read device
11/29/2001US20010046153 Semiconductor integrated circuit
11/29/2001US20010046150 Symmetric architecture for memory cells having widely spread metal bit lines
11/29/2001US20010046149 Semiconductor storage device having arrangement for controlling activation of sense amplifiers
11/29/2001US20010045969 Shutter ink jet
11/29/2001US20010045856 Delay circuit having low operating environment dependency
11/29/2001US20010045852 Clock control method and circuit
11/29/2001US20010045851 Clock control method and circuit
11/29/2001US20010045841 Semiconductor integrated circuit, test method for the same, and recording device and communication equipment having the same
11/29/2001US20010045595 Ferroelectric memory transistor with resistively coupled floating gate
11/29/2001US20010045583 Semiconductor memory device capable of performing stable operation for noise while preventing increase in chip area
11/29/2001US20010045579 Semiconductor device with reduced current consumption in standby state
11/29/2001US20010045574 Read amplifier circuit for high-speed reading and semiconductor memory device employing the read amplifier circuit
11/29/2001US20010045569 Potential detector and semiconductor integrated circuit
11/29/2001DE10124112A1 Semiconducting memory for high speed operation has word drive circuit driving word line in response to word reset signal, main word signal and word decoder signal
11/29/2001DE10110157A1 Halbleitervorrichtung mit verringertem Stromverbrauch im Standby-Zustand Semiconductor device with reduced power consumption in standby mode
11/29/2001DE10058227A1 Halbleiterspeicherbauelement, Durchlass-/Zwischenspeichereinheit hierfür und zugehöriges Datenübertragungsverfahren A semiconductor memory device, transmission / latch unit therefor, and associated data transfer process
11/29/2001CA2409214A1 Block ram having multiple configurable write modes for use in a field programmable gate array
11/28/2001EP1158403A1 FPGA with configurable clock lines
11/28/2001EP1158402A1 FPGA with column set/reset lines
11/28/2001EP1157388A1 Storage cell arrangement and method for producing the same
11/28/2001EP1157387A1 Full page increment/decrement burst for ddr sdram/sgram
11/28/2001EP1157386A1 Nanocapsules containing charged particles, their uses and methods of forming the same
11/28/2001EP0929901B1 Memory array, memory cell, and sense amplifier test and characterization
11/28/2001EP0929900B1 Data retention test for static memory cell
11/28/2001EP0929898B1 Memory block select using multiple word lines to address a single memory cell row
11/28/2001EP0929896B1 Memory including resistor bit-line loads
11/28/2001EP0929895B1 Active power supply filter
11/28/2001EP0806045B1 Decoded wordline driver with positive and negative voltage modes
11/28/2001EP0590651B1 Dynamic random access memory device having power supply system appropriately biasing switching transistors and storage capacitors in burn-in testing process
11/28/2001CN1324486A Semiconductor device
11/28/2001CN1075651C Spin valve magnet resistive sensor and magnetic recording system using the sensor
11/27/2001US6324602 Advanced input/output interface for an integrated circuit device using two-level to multi-level signal conversion
11/27/2001US6324436 Method for optimizing cost of manufacturing memory arrays
11/27/2001US6324239 Method and apparatus for a 1 of 4 shifter
11/27/2001US6324122 RAM synchronized with a signal
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