Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
01/2002
01/01/2002US6335874 Symmetric segmented memory array architecture
01/01/2002US6335873 Semiconductor integrated circuit device
01/01/2002US6335652 Method and apparatus for the replacement of non-operational metal lines in DRAMS
01/01/2002US6335554 Semiconductor Memory
01/01/2002CA2245271C Method for controlling non-volatile semiconductor memory system
12/2001
12/27/2001WO2001099153A2 A negative differential resistance device and method of operating same
12/27/2001WO2001052265A3 Decoder circuit
12/27/2001WO2001045161B1 Nonvolatile memory and method of driving nonvolatile memory
12/27/2001WO2000060603A9 Dynamic random access memories with hidden refresh and utilizing one-transistor, one-capacitor cells, systems and methods
12/27/2001US20010056521 Information processing system with memory element performance-dependent memory control
12/27/2001US20010055822 Semiconductor memory and method for driving the same
12/27/2001US20010055236 Semiconductor memory that enables high speed operation
12/27/2001US20010055235 Semiconductor memory device
12/27/2001US20010055232 Serial access memory and data write/read method
12/27/2001US20010055229 Semiconductor memory device and testing system and testing method
12/27/2001US20010055223 Nonvolatile semiconductor memory
12/27/2001US20010055222 Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell
12/27/2001US20010055220 Voltage regulation device for reference cell of a dynamic random access memory, reference cell, memory and associated process
12/27/2001US20010055218 256 meg dynamic random access memory
12/27/2001US20010055022 Serial access memory and data write/read method
12/27/2001US20010054922 Delay locked loop circuit capable of adjusting phase of clock with high precision
12/27/2001US20010054920 Semiconductor device capable of internally adjusting delayed amount of a clock signal
12/27/2001US20010054917 Driver circuit, receiver circuit, and semiconductor integrated circuit device
12/27/2001US20010054909 Integrated circuit device having a burn-in mode for which entry into and exit from can be controlled
12/27/2001US20010054886 Input circuit and output circuit
12/27/2001US20010054760 Semiconductor integrated circuit
12/27/2001US20010054737 Semiconductor memory device using only single-channel transistor to apply voltage to selected word line
12/27/2001US20010054732 Semiconductor memory and method for driving the same
12/26/2001CN1328700A Memory cell arrangement
12/26/2001CN1328688A Circuir for generating reference voltage for reading out from ferroelectric memory
12/26/2001CN1328687A Method and apparatus to control temp of component
12/25/2001US6334190 System for the manipulation of secure data
12/25/2001US6334167 System and method for memory self-timed refresh for reduced power consumption
12/25/2001US6334136 Dynamic 3-level partial result merge adder
12/25/2001US6333895 Clock synchronous semiconductor device having a reduced clock access time
12/25/2001US6333894 Semiconductor storage device
12/25/2001US6333893 Method and apparatus for crossing clock domain boundaries
12/25/2001US6333892 Synchronous semiconductor memory device capable of selecting column at high speed
12/25/2001US6333890 Memory device with a plurality of common data buses
12/25/2001US6333889 Logic-merged semiconductor memory having high internal data transfer rate
12/25/2001US6333888 Semiconductor memory device
12/25/2001US6333886 Self-refresh controlling apparatus
12/25/2001US6333884 Semiconductor memory device permitting improved integration density and reduced accessing time
12/25/2001US6333883 Destructive read type memory circuit, restoring circuit for the same and sense amplifier
12/25/2001US6333882 Equilibration/pre-charge circuit for a memory device
12/25/2001US6333881 Semiconductor memory
12/25/2001US6333879 Semiconductor device operable in a plurality of test operation modes
12/25/2001US6333878 Semiconductor memory device having program circuit
12/25/2001US6333877 Static type semiconductor memory device that can suppress standby current
12/25/2001US6333875 Semiconductor circuit with adjustment of double data rate data latch timings
12/25/2001US6333874 Semiconductor memory device having normal and standby modes, semiconductor integrated circuit and mobile electronic unit
12/25/2001US6333873 Semiconductor memory device with an internal voltage generating circuit
12/25/2001US6333871 Nonvolatile semiconductor memory including a controller for providing an improved reprogram operation
12/25/2001US6333870 Nonvolatile ferroelectric memory device and method for driving same
12/25/2001US6333869 Semiconductor memory device with readily changeable memory capacity
12/25/2001US6333866 Semiconductor device array having dense memory cell array and heirarchical bit line scheme
12/25/2001US6333864 Power supply adjusting circuit and a semiconductor device using the same
12/25/2001US6333671 Sleep mode VDD detune for power reduction
12/25/2001US6333670 Semiconductor device capable of stably generating internal voltage with low supply voltage
12/25/2001US6333669 Voltage converting circuit allowing control of current drivability in accordance with operational frequency
12/25/2001US6333668 Semiconductor device for suppressing current peak flowing to/from an external power supply
12/25/2001US6333658 Analog synchronization circuit
12/25/2001US6333656 Flip-flops
12/25/2001US6333571 MOS integrated circuit device operating with low power consumption
12/25/2001US6333530 Semiconductor memory device having redundancy function
12/25/2001US6333517 Semiconductor integrated circuit device equipped with power make-up circuit used in burn-in test after packaging and method for testing the same
12/25/2001US6333214 Memory of multilevel quantum dot structure and method for fabricating the same
12/20/2001WO2001097373A2 Multiple output current mirror with improved accuracy
12/20/2001WO2001097227A1 Non-volatile ferromagnetic memory having sensor circuitry shared with its state change circuitry
12/20/2001WO2001097226A2 Semiconductor memory having segmented row repair
12/20/2001WO2001050473A3 Arrangement for voltage supply to a volatile semiconductor memory
12/20/2001US20010054165 Memory device having redundant cells
12/20/2001US20010054135 Memory control technique
12/20/2001US20010053195 Semiconductor device
12/20/2001US20010053106 Semiconductor memory device
12/20/2001US20010053104 Reference signal generation for magnetic random access memory devices
12/20/2001US20010053103 Semiconductor memory with built-in cache
12/20/2001US20010053102 Device with integrated SRAM memory and method of testing such a device
12/20/2001US20010053101 Semiconductor memory having segmented row repair
12/20/2001US20010053099 Semiconductor integrated circuit device capable of ensuring reliability of transistor driving high voltage
12/20/2001US20010053098 Semiconductor memory device having reduced current consumption at internal boosted potential
12/20/2001US20010053090 Semiconductor storage device
12/20/2001US20010053089 Circuits and methods for a static random access memory using vertical transistors
12/20/2001US20010053088 Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device
12/20/2001US20010053087 Method for driving semiconductor memory
12/20/2001US20010053086 Semiconductor memory device with memory test circuit
12/20/2001US20010052808 Clock generation circuit generating internal clock of small variation in phase difference from external clock, and semiconductor memory device including such clock generation circuit
12/20/2001US20010052794 Semiconductor circuit device having active and standby states
12/20/2001US20010052792 Semiconductor integrated circuit device including logic gate that attains reduction of power consumption and high-speed operation
12/20/2001US20010052784 Voltage detecting circuit for semiconductor memory device
12/20/2001US20010052633 Semiconductor device
12/20/2001US20010052624 SRAM with write-back on read
12/20/2001US20010052610 Reduced topography DRAM cell fabricated using a modified logic process and method for operating same
12/20/2001US20010052602 Synchronous semiconductor memory device allowing data to be satisfactorily rewritten therein
12/20/2001US20010052599 Semiconductor memory device including plurality of global data lines in parallel arrangement with low parasitic capacitance, and fabrication method thereof
12/20/2001DE10063623A1 Semiconductor memory has select drive circuit which selectively drives dummy word line transistor, while operating in test mode
12/20/2001DE10036140C1 Non-destructive read-out of MRAM memory cells involves normalizing actual cell resistance, comparing normalized and normal resistance values, detecting content from the result
12/19/2001EP1164595A1 Semiconductor device
12/19/2001EP1164594A1 Semiconductor storage device
12/19/2001EP1164593A1 Voltage regulator for a reference cell in a dynamic memory, reference cell, memory and method thereof
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