Patents
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
02/2002
02/06/2002CN1334567A MRAM memory unit
02/06/2002CN1334466A Modular structure for testing momery in testing system based on event
02/05/2002US6345381 Method and apparatus for a logic circuit design tool
02/05/2002US6345348 Memory system capable of supporting different memory devices and a memory device used therefor
02/05/2002US6345334 High speed semiconductor memory device capable of changing data sequence for burst transmission
02/05/2002US6345011 Input/output line structure of a semiconductor memory device
02/05/2002US6345010 Semiconductor storage device
02/05/2002US6345009 Apparatus and method for refreshing subsets of memory devices in a memory system
02/05/2002US6345007 Prefetch and restore method and apparatus of semiconductor memory device
02/05/2002US6345006 Memory circuit with local isolation and pre-charge circuits
02/05/2002US6345002 RAS monitor circuit and field memory using the same
02/05/2002US6344998 Electrically alterable non-volatile memory with N-Bits per cell
02/05/2002US6344996 Semiconductor memory device
02/05/2002US6344994 Data retention characteristics as a result of high temperature bake
02/05/2002US6344993 Dual floating gate EEPROM cell array with steering gates shared by adjacent cells
02/05/2002US6344992 SRAM operating with a reduced power dissipation
02/05/2002US6344991 Nonvolatile semiconductor memory device
02/05/2002US6344990 DRAM for storing data in pairs of cells
02/05/2002US6344771 Step-down power-supply circuit
02/05/2002US6344765 Signal transmission with reduced ringing of signals
02/05/2002US6344764 Semiconductor integrated circuit device
02/05/2002US6344763 Semiconductor integrated circuit device that can suppress generation of signal skew between data input/output terminals
02/05/2002US6344760 Sense amplifier drive circuit
01/2002
01/31/2002WO2002009206A1 Electrically programmable memory element
01/31/2002WO2002009126A2 Spin valve structure
01/31/2002WO2002009119A1 Inner voltage level control circuit, semiconductor storage, and method for controlling them
01/31/2002WO2002009118A1 Semiconductor memory and control method
01/31/2002WO2002009117A1 Programmable molecular device
01/31/2002WO2002009116A1 High-performance high-density cmos sram cell
01/31/2002WO2002009115A1 Cmos sram cell with prescribed power-on data state
01/31/2002WO2001075891A3 Current conveyor and method for readout of mtj memories
01/31/2002US20020013004 Solid-state memory with magnetic storage cells
01/31/2002US20020012285 Semiconductor memory device
01/31/2002US20020012284 Semiconductor memory device and method for accessing memory cell
01/31/2002US20020012276 Semiconductor memory device having read data multiplexer
01/31/2002US20020012269 MRAM architectures for increased write selectivity
01/31/2002US20020012268 MRAM architectures for increased write selectivity
01/31/2002US20020012267 Non-volatile memory device
01/31/2002US20020012266 Random access semiconductor memory with reduced signal overcoupling
01/31/2002US20020012265 Semiconductor storage device
01/31/2002US20020012264 Ferroelectric non-volatile memory device
01/31/2002US20020012263 Semiconductor memory device
01/31/2002US20020012262 High-speed low-power semiconductor memory architecture
01/31/2002US20020011994 Matrix display apparatus, matrix display control apparatus, and matrix display drive apparatus
01/31/2002US20020011894 256 Meg dynamic random access memory
01/31/2002US20020011893 Substrate electric potential sense circuit and substrate electric potential generator circuit
01/31/2002US20020011883 Multi-power semiconductor integrated circuit device
01/31/2002US20020011876 Current sense amplifiers enabling amplification of bit line voltages provided by bit line sense amplifiers
01/31/2002US20020011826 Semiconductor integrated circuit device capable of stably generating internal voltage
01/31/2002US20020011610 Semiconductor memory device having pairs of bit lines arranged on both sides of memory cells
01/31/2002DE10133281A1 Memory device e.g. multiport SRAM used in integrated circuit, has switch connected between write data bit line and storage node, which conducts only when both write word line and write control line are active
01/31/2002DE10035636A1 Circuit, especially semiconducting circuit, memory device, DRAM element or similar has protection device that analyzes input signal for noise, suppresses signal transfer if noise is present.
01/31/2002DE10034925A1 Dekodiervorrichtung Decoding
01/31/2002DE10034255A1 Schaltungsanordnung zum Lesen und Schreiben von Information an einem Speicherzellenfeld Circuit arrangement for reading and writing information on a memory cell array
01/31/2002DE10032236A1 Circuit for changing over receiver circuit, especially in DRAM memory, supplies receiver control current continuously via switches in working mode, periodically in standby mode
01/31/2002CA2417462A1 Programmable molecular device
01/30/2002EP1176609A2 Testing of multilevel semiconductor memory
01/30/2002EP1176605A2 Integrated memory with magnetoresistive memory cells
01/30/2002EP1176604A2 Method for testing a plurality of word lines in a semiconductor memory device
01/30/2002EP1176601A1 Semiconductor memory and method for driving the same
01/30/2002EP1176600A1 Method and device for noiselesss reading of memory cells of a MRAM memory
01/30/2002EP1176599A2 Circuit device for switching a receiver circuit, especially in DRAM memories
01/30/2002EP1175679A1 Data balancing scheme in solid state storage devices
01/30/2002EP1151365A4 Rapid on chip voltage generation for low power integrated circuits
01/30/2002EP0858032B1 Circuit for repairing defective bit in semiconductor memory device and repairing method
01/30/2002CN1333564A Memory
01/30/2002CN1333563A Method for driving semiconductor memory
01/30/2002CN1333538A Arbitrary selective access semiconductor memor capable of reducing signal overcoupling
01/30/2002CN1078730C Semiconductor storage device
01/29/2002US6343366 BIST circuit for LSI memory
01/29/2002US6343048 Operation mode setting circuit of semiconductor memory device and method for setting thereof
01/29/2002US6343046 Semiconductor integrated circuit device
01/29/2002US6343045 Methods to reduce the effects of leakage current for dynamic circuit elements
01/29/2002US6343044 Super low-power generator system for embedded applications
01/29/2002US6343043 Dynamic random access memory
01/29/2002US6343042 DRAM core refresh with reduced spike current
01/29/2002US6343041 Semiconductor integrated circuit
01/29/2002US6343039 Data transfer circuit
01/29/2002US6343038 Semiconductor memory device of shared sense amplifier system
01/29/2002US6343037 Column redundancy circuit for semiconductor memory
01/29/2002US6343036 Multi-bank dynamic random access memory devices having all bank precharge capability
01/29/2002US6343035 Semiconductor device allowing switchable use of internal data buses
01/29/2002US6343034 Electrically alterable non-volatile memory with n-bits per cell
01/29/2002US6343033 Variable pulse width memory programming
01/29/2002US6343032 Non-volatile spin dependent tunnel junction circuit
01/29/2002US6342797 Delayed locked loop clock generator using delay-pulse-delay conversion
01/29/2002US6342716 Semiconductor device having dot elements as floating gate
01/29/2002US6342713 Method of operating a magnetoelectronic device
01/29/2002US6342710 Semiconductor integrated circuit
01/29/2002US6342408 Method of manufacturing semiconductor memory device
01/29/2002CA2301283C A ferroelectric data processing device
01/24/2002WO2002007166A2 Mram architectures for increased write selectivity
01/24/2002US20020010884 Test method for switching to redundant circuit in SRAM pellet
01/24/2002US20020010832 Memory device which receives write masking and automatic precharge information
01/24/2002US20020010829 Buffering circuit in a semiconductor memory device
01/24/2002US20020009840 High density giant magnetoresistive memory cell
01/24/2002US20020009014 Circuit for eliminating idle cycles in a memory device
01/24/2002US20020009012 Semiconductor memory device, and method of controlling the same
01/24/2002US20020009010 Dynamic random access memory
01/24/2002US20020009008 Process for controlling a read access for a dynamic random access memory and corresponding memory