| Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008) |
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| 01/24/2002 | US20020009004 Semiconductor memory device enabling test of timing standard for strobe signal and data signal with ease, and subsidiary device and testing device thereof |
| 01/24/2002 | US20020008999 Semiconductor integrated circuit device operating with low power consumption |
| 01/24/2002 | US20020008997 High speed interface type semiconductor memory device |
| 01/24/2002 | US20020008991 Semiconductor device, data processing system and a method for changing threshold of a non-volatile memory cell |
| 01/24/2002 | US20020008990 Nonvolatile semiconductor memory device |
| 01/24/2002 | US20020008989 MRAM memory cell |
| 01/24/2002 | US20020008988 Magnetic memory |
| 01/24/2002 | US20020008987 Magnetic random access memory |
| 01/24/2002 | US20020008986 Data reading method and semiconductor memory device |
| 01/24/2002 | US20020008984 256 Meg dynamic random access memory |
| 01/24/2002 | US20020008566 Internal Voltage generation circuit |
| 01/24/2002 | US20020008564 Decoder element for generating an output signal having three different potentials and an operating method for the decoder element |
| 01/24/2002 | US20020008560 Variable delay circuit and semiconductor integrated circuit device |
| 01/24/2002 | US20020008558 Clock generation circuit, control method of clock generation circuit and semiconductor memory device |
| 01/24/2002 | US20020008555 Semiconductor integrated circuit including a plurality of macros that can be operated although their operational voltages are different from each other |
| 01/24/2002 | US20020008550 Sense amplifier of semiconductor integrated circuit |
| 01/24/2002 | US20020008549 Pseudo-differential current sense amplifier with hysteresis |
| 01/24/2002 | US20020008539 Bus system and circuit board |
| 01/24/2002 | US20020008502 Voltage downconverter circuit capable of reducing current consumption while keeping response rate |
| 01/24/2002 | US20020008500 Semiconductor integrated circuit and method for generating internal supply voltage |
| 01/24/2002 | US20020008255 Semiconductor device |
| 01/24/2002 | US20020008254 Semiconductor device |
| 01/24/2002 | DE10033486A1 Integrated memory (MRAM), whose memory cells contain magnetoresistive memory effect |
| 01/24/2002 | DE10033441A1 Circuit generating correctioon signals is integrated, dynamic semiconductor memories (DRAM) |
| 01/24/2002 | DE10032412A1 Electronic storage element used in CMOS technology comprises carbon nanotubes arranged skew to each other or crossing each other so that an electrical coupling is produced between the tubes |
| 01/24/2002 | DE10032277A1 MRAM-Anordnung MRAM array |
| 01/24/2002 | DE10032275A1 Integrierter Speicher mit Speicherzellen mit magnetoresistivem Speichereffekt und Verfahren zum Betrieb eines solchen Speichers Integrated memory having memory cells with magnetoresistive storage effect and methods of operation of such a memory |
| 01/24/2002 | DE10032274A1 Magnetoresistive random access memory controls sense amplifier such that column lines not connected to selected memory cells, are electrically isolated in sense amplifier for selectively reading and writing data signal |
| 01/24/2002 | DE10032273A1 Verfahren und Anordnung zur Kompensation von parasitären Stromverlusten Method and apparatus for compensating for parasitic power losses |
| 01/24/2002 | DE10032272A1 Strom-Treiberanordnung für MRAM Current driver configuration for MRAM |
| 01/24/2002 | DE10032271A1 MRAM-Anordnung MRAM array |
| 01/24/2002 | DE10032241A1 Switching circuit for logging process registrations and status data is based on ferro RAM memory |
| 01/24/2002 | DE10031948A1 DRAM interface has latency setting unit for adjusting latency to fixed value |
| 01/24/2002 | DE10031947A1 Schaltungsanordnung zum Ausgleich unterschiedlicher Spannungen auf Leitungszügen in integrierten Halbleiterschaltungen Circuitry to compensate for different voltages on line trains in semiconductor integrated circuits |
| 01/23/2002 | EP1174925A2 Write conductor layout for magnetic memory |
| 01/23/2002 | EP1174924A2 MRAM-cell |
| 01/23/2002 | EP1174883A2 Method for driving semiconductor memory |
| 01/23/2002 | EP1174882A1 MRAM memory device |
| 01/23/2002 | EP1174880A1 Data transfer system for transferring data in synchronization with system clock and synchronous semiconductor memory |
| 01/23/2002 | EP1105881A4 Techniques for analog and multilevel storage using integrated circuit technology |
| 01/23/2002 | EP0935802B1 Staggered row line firing in a single ras cycle |
| 01/23/2002 | EP0914659A4 Combined program and data nonvolatile memory with concurrent program-read/data write capability |
| 01/23/2002 | CN1332458A Operation method of ferroelectric memory |
| 01/23/2002 | CN1078378C Semiconductor memory device having plurality of rwo address strobe signals |
| 01/22/2002 | US6341100 Semiconductor integrated circuit having circuit for writing data to memory cell |
| 01/22/2002 | US6341098 Semiconductor integrated circuit device having hierarchical power source arrangement |
| 01/22/2002 | US6341097 Selective address space refresh mode |
| 01/22/2002 | US6341095 Apparatus for increasing pulldown rate of a bitline in a memory device during a read operation |
| 01/22/2002 | US6341090 Method for repairing semiconductor integrated circuit device |
| 01/22/2002 | US6341089 Semiconductor memory device allowing effective detection of leak failure |
| 01/22/2002 | US6341088 Dynamic random access memory in switch MOSFETs between sense amplifiers and bit lines |
| 01/22/2002 | US6341087 Semiconductor device |
| 01/22/2002 | US6341086 Semiconductor memory circuit including a data output circuit |
| 01/22/2002 | US6341084 Magnetic random access memory circuit |
| 01/22/2002 | US6341083 CMOS SRAM cell with PFET passgate devices |
| 01/22/2002 | US6341082 Ferroelectric memory capable of suppressing deterioration of dummy cells and drive method therefor |
| 01/22/2002 | US6341081 Circuit for driving nonvolatile ferroelectric memory |
| 01/22/2002 | US6341080 Hall effect ferromagnetic random access memory device and its method of manufacture |
| 01/22/2002 | US6341053 Magnetic tunnel junction elements and their fabrication method |
| 01/22/2002 | US6340904 Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal |
| 01/22/2002 | US6340902 Semiconductor device having multiple power-supply nodes and capable of self-detecting power-off to prevent erroneous operation |
| 01/22/2002 | US6340845 Memory package implementing two-fold memory capacity and two different memory functions |
| 01/22/2002 | US6340222 Utilizing venting in a MEMS liquid pumping system |
| 01/17/2002 | WO2002005470A2 Magnetoresistive trimming of gmr circuits |
| 01/17/2002 | WO2002005318A2 High density giant magnetoresistive memory cell |
| 01/17/2002 | WO2002005288A1 A method for performing write and read operations in a passive matrix memory, and apparatus for performing the method |
| 01/17/2002 | WO2002005287A1 Addressing of memory matrix |
| 01/17/2002 | WO2002005286A1 Magnetic memory |
| 01/17/2002 | WO2002005284A1 Multilevel memory access method |
| 01/17/2002 | WO2002005283A1 Method and apparatus for synchronization of row and column access operations |
| 01/17/2002 | WO2002005282A1 A method and apparatus for simultaneous differential data sensing and capture in a high speed memory |
| 01/17/2002 | WO2002005281A2 A high speed dram architecture with uniform access latency |
| 01/17/2002 | WO2002005268A2 All metal giant magnetoresistive memory |
| 01/17/2002 | WO2001051188A3 High-density non-volatile memory devices incorporating thiol-derivatized porphyrin trimers |
| 01/17/2002 | US20020007480 Circuit configuration for equalizing different voltages on line runs in integrated semiconductor circuits |
| 01/17/2002 | US20020006073 Decoding circuit for controlling activation of wordlines in a semiconductor memory device |
| 01/17/2002 | US20020006072 Memory device |
| 01/17/2002 | US20020006071 Semiconductor memory device having an SRAM and a DRAM on a single chip |
| 01/17/2002 | US20020006070 High performance memory architecture |
| 01/17/2002 | US20020006069 Semiconductor memory device with reduced standby current |
| 01/17/2002 | US20020006068 Method and configuration for compensating for parasitic current losses |
| 01/17/2002 | US20020006067 Integrated circuit memory devices having efficient multi-row address test capability and methods of operating same |
| 01/17/2002 | US20020006064 Semiconductor memory device and method of checking same for defect |
| 01/17/2002 | US20020006062 Semiconductor device |
| 01/17/2002 | US20020006061 Integrated memory having memory cells with a magnetoresistive storage property |
| 01/17/2002 | US20020006058 Magnetic memory device |
| 01/17/2002 | US20020006057 Memory device |
| 01/17/2002 | US20020006056 Selective device coupling |
| 01/17/2002 | US20020006055 Selective device coupling |
| 01/17/2002 | US20020006054 Semiconductor integrated circuit and nonvolatile memory element |
| 01/17/2002 | US20020006053 Ferroelectric memory |
| 01/17/2002 | US20020006052 Method for driving semiconductor memory |
| 01/17/2002 | US20020006050 Memory architecture with refresh and sense amplifiers |
| 01/17/2002 | US20020005758 Signal conversion circuit for stable differential amplification and semiconductor device provided with the same as input buffer |
| 01/17/2002 | US20020005746 Internal clock generator generating an internal clock signal having a phase difference with respect to an external clock signal |
| 01/17/2002 | US20020005737 256 Meg dynamic random access memory |
| 01/17/2002 | US20020005590 Digit line architecture for dynamic memory |
| 01/17/2002 | DE10134495A1 Memory component and processing method for 3-D computer objects for use in 3-D graphics applications in which object depth data are rapidly changed by comparison of new external data with internal existing data |
| 01/17/2002 | DE10053206C1 Logic circuit device uses magnetoresistive element with magnetizable soft magnetic layer and selective perpendicular magnetic field for alteration of logic function |
| 01/17/2002 | DE10030234A1 Integrierter Speicher mit Speicherzellen mit magnetoresistivem Speichereffekt Integrated memory having memory cells with a magnetoresistive memory effect |