| Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008) |
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| 02/04/2003 | US6515921 Semiconductor storage device having redundancy circuit for replacement of defect cells under tests |
| 02/04/2003 | US6515918 Semiconductor device |
| 02/04/2003 | US6515916 Column switch in memory device and cache memory using the same |
| 02/04/2003 | US6515915 Circuits and methods for outputting multi-level data through a single input/output pin |
| 02/04/2003 | US6515914 Memory device and method having data path with multiple prefetch I/O configurations |
| 02/04/2003 | US6515913 Semiconductor memory device and defect remedying method thereof |
| 02/04/2003 | US6515897 Magnetic random access memory using a non-linear memory element select mechanism |
| 02/04/2003 | US6515896 Memory device with short read time |
| 02/04/2003 | US6515895 Non-volatile magnetic register |
| 02/04/2003 | US6515894 Semiconductor memory apparatus, semiconductor apparatus, data processing apparatus and computer system |
| 02/04/2003 | US6515893 Source pulsed, low voltage CMOS SRAM cell for fast, stable operation |
| 02/04/2003 | US6515892 Semiconductor integrated circuit device |
| 02/04/2003 | US6515891 Random access memory with hidden bits |
| 02/04/2003 | US6515890 Integrated semiconductor memory having memory cells with a ferroelectric memory property |
| 02/04/2003 | US6515889 Junction-isolated depletion mode ferroelectric memory |
| 02/04/2003 | US6515887 Semiconductor memory device |
| 02/04/2003 | US6515461 Voltage downconverter circuit capable of reducing current consumption while keeping response rate |
| 02/04/2003 | US6515341 Magnetoelectronics element having a stressed over-layer configured for alteration of the switching energy barrier |
| 02/04/2003 | US6514823 Method of making loadless four-transistor memory cell with different gate insulation thicknesses for N-channel drive transistors and P-channel access transistors |
| 02/04/2003 | US6514820 Method for forming single electron resistor memory |
| 02/04/2003 | US6514818 Nonvolatile ferroelectric memory without a separate cell plate line and method of manufacturing the same |
| 02/04/2003 | US6513908 Pusher actuation in a printhead chip for an inkjet printhead |
| 01/30/2003 | WO2003009385A1 Semiconductor device, semiconductor storage device and production methods therefor |
| 01/30/2003 | WO2003009304A2 Duty-cycle-efficient sram cell test |
| 01/30/2003 | WO2003009303A1 Surface-enhanced raman optical data storage (serods) with papallel signal transfer |
| 01/30/2003 | WO2003009302A1 Semiconductor memory device |
| 01/30/2003 | WO2002017323A3 Synchronized write data on a high speed memory bus |
| 01/30/2003 | US20030023928 Manufacturing test for a fault tolerant magnetoresistive solid-state storage device |
| 01/30/2003 | US20030023927 Method for error correction decoding in a magnetoresistive solid-state storage device |
| 01/30/2003 | US20030023926 Magnetoresistive solid-state storage device and data storage methods for use therewith |
| 01/30/2003 | US20030023925 Manufacturing test for a fault tolerant magnetoresistive solid-state storage device |
| 01/30/2003 | US20030023924 Data storage method for use in a magnetoresistive solid-state storage device |
| 01/30/2003 | US20030023923 Error correction coding and decoding in a solid-state storage device |
| 01/30/2003 | US20030023922 Fault tolerant magnetoresistive solid-state storage device |
| 01/30/2003 | US20030023911 Method for error correction decoding in an MRAM device (historical erasures) |
| 01/30/2003 | US20030023805 Memory module and system, an information processing apparatus and a mehtod of use |
| 01/30/2003 | US20030023788 Data input/output device, memory system, data input/output circuit, and data input/output method |
| 01/30/2003 | US20030022476 Data bus architecture for integrated circuit devices having embedded dynamic random access memory (DRAM) with a large aspect ratio providing reduced capacitance and power requirements |
| 01/30/2003 | US20030022427 DRAM cell refreshment method and circuit |
| 01/30/2003 | US20030021908 Gas cluster ion beam process for smoothing MRAM cells |
| 01/30/2003 | US20030021177 Synchronous semiconductor memory device and method of processing data thereof |
| 01/30/2003 | US20030021176 Programmable address logic for solid state diode-based memory |
| 01/30/2003 | US20030021175 Low power type Rambus DRAM |
| 01/30/2003 | US20030021173 Sense amplifier for memory device |
| 01/30/2003 | US20030021168 Semiconductor storage device and information apparatus using the same |
| 01/30/2003 | US20030021163 Semiconductor memory device and information device |
| 01/30/2003 | US20030021162 Semiconductor memory device including internal power circuit having tuning function |
| 01/30/2003 | US20030021161 Sense amplifier threshold compensation |
| 01/30/2003 | US20030021159 Compact analog-multiplexed global sense amplifier for rams |
| 01/30/2003 | US20030021156 Semiconductor memory device and storage method thereof |
| 01/30/2003 | US20030021149 Multi-bit-per-cell flash EEPROM memory with refresh |
| 01/30/2003 | US20030021147 Optically programmable address logic for solid state diode-based memory |
| 01/30/2003 | US20030021146 Structure and method for transverse field enhancement |
| 01/30/2003 | US20030021145 Memory device with short read time |
| 01/30/2003 | US20030021144 Static memory having self-timing circuit |
| 01/30/2003 | US20030021143 Ferroelectric memory and method for reading the same |
| 01/30/2003 | US20030021140 Semiconductor memory |
| 01/30/2003 | US20030021138 256 meg dynamic random access memory |
| 01/30/2003 | US20030021137 Method for data communication between a plurality of semiconductor modules and a controller module and semiconductor module configured for that purpose |
| 01/30/2003 | US20030020534 Voltage generating circuits and methods including shared capacitors |
| 01/30/2003 | US20030020105 Ferroelectric memory |
| 01/30/2003 | US20030020097 Memory device with divided bit-line architecture |
| 01/30/2003 | US20030020095 Semiconductor integrated circuit with voltage down converter adaptable for burn-in testing |
| 01/30/2003 | US20030020093 Semiconductor integrated circuit |
| 01/29/2003 | EP1280205A2 Semiconductor memory device |
| 01/29/2003 | EP1279180A2 Tunable devices incorporating bicu3 ti3 feo12 |
| 01/29/2003 | EP1163678B1 Integrated memory with memory cells which each have a ferroelectric memory transistor |
| 01/29/2003 | CN1393887A Resistance cross point array connecting storage location |
| 01/29/2003 | CN1100324C Semiconductor storage device with improved stage power source line structure |
| 01/28/2003 | US6513081 Memory device which receives an external reference voltage signal |
| 01/28/2003 | US6512719 Semiconductor memory device capable of outputting and inputting data at high speed |
| 01/28/2003 | US6512718 Circuit for controlling wordline in SRAM |
| 01/28/2003 | US6512717 Semiconductor memory device having a relaxed pitch for sense amplifiers |
| 01/28/2003 | US6512716 Memory device with support for unaligned access |
| 01/28/2003 | US6512715 Semiconductor memory device operating with low power consumption |
| 01/28/2003 | US6512714 Semiconductor memory device equipped with dummy cells |
| 01/28/2003 | US6512708 Placement and routing for wafer scale memory |
| 01/28/2003 | US6512705 Method and apparatus for standby power reduction in semiconductor devices |
| 01/28/2003 | US6512704 Data strobe receiver |
| 01/28/2003 | US6512690 High sensitivity common source amplifier MRAM cell, memory array and read/write scheme |
| 01/28/2003 | US6512689 MRAM without isolation devices |
| 01/28/2003 | US6512688 Device for evaluating cell resistances in a magnetoresistive memory |
| 01/28/2003 | US6512686 Ferroelectric storage device and test method thereof |
| 01/28/2003 | US6512274 CMOS-process compatible, tunable NDR (negative differential resistance) device and method of operating same |
| 01/23/2003 | WO2003007306A2 Method and system for banking register file memory arrays |
| 01/23/2003 | WO2003007305A1 Semiconductor storage, mobile electronic device, and detachable storage |
| 01/23/2003 | WO2003007304A2 Magnetic memory unit and magnetic memory array |
| 01/23/2003 | WO2003007303A2 Memory device having different burst order addressing for read and write operations |
| 01/23/2003 | WO2003007234A2 Information register |
| 01/23/2003 | WO2002049035A3 Memory device and method for the operation of the same |
| 01/23/2003 | WO2001091296A3 Block ram having multiple configurable write modes for use in a field programmable gate array |
| 01/23/2003 | US20030018848 Memory device interface |
| 01/23/2003 | US20030018846 Method and system for fast memory initialization or diagnostics |
| 01/23/2003 | US20030018845 Memory device having different burst order addressing for read and write operations |
| 01/23/2003 | US20030017627 Stacked ferroelectric memory device and method of making same |
| 01/23/2003 | US20030016614 SERODS optical data storage with parallel signal transfer |
| 01/23/2003 | US20030016583 Semiconductor memory device with reduced standby current |
| 01/23/2003 | US20030016577 6f2 dram array with apparatus for stress testing an isolation gate and method |
| 01/23/2003 | US20030016576 Nonvolatile memory device and refreshing method |
| 01/23/2003 | US20030016574 Method of adjusting semiconductor buffer capability of semiconductor device, electronic system, and semiconductor device |